Digital Logic Design (DLD) Complete Course \u2013 University Level \u2013 Pak Notes Hub<\/title>\r\n <link href=\"https:\/\/fonts.googleapis.com\/css2?family=Inter:wght@400;500;600;700&family=Fira+Code:wght@400;500&display=swap\" rel=\"stylesheet\"\/>\r\n <style>\r\n *, *::before, *::after { box-sizing: border-box; margin: 0; padding: 0; }\r\n :root {\r\n --green:#1a7a4a; --green-dark:#145f38; --green-light:#e8f5ee;\r\n --teal:#17a589; --accent:#f0b127; --dark:#1c2833; --mid:#566573;\r\n --light:#f4f6f7; --code-bg:#f0f4f8; --code-border:#2e86c1;\r\n --note-bg:#fef9e7; --note-border:#f0b127; --white:#ffffff;\r\n --radius:10px; --shadow:0 4px 24px rgba(26,122,74,.10);\r\n }\r\n html { scroll-behavior:smooth; }\r\n body { font-family:'Inter',sans-serif; background:#f2f6f3; color:var(--dark); line-height:1.7; font-size:15px; }\r\n\r\n \/* NAV *\/\r\n nav { position:sticky; top:0; z-index:100; background:var(--green-dark); padding:0 2rem; display:flex; align-items:center; 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class=\"hero-tag\">\u26a1 University \/ College Level \u2014 BS Computer Science \/ Computer Engineering \/ Electrical Engineering<\/div>\r\n <h1>Digital Logic Design<br\/><span>Complete Course<\/span><\/h1>\r\n <p>Number Systems \u00b7 Boolean Algebra \u00b7 Logic Gates \u00b7 Combinational & Sequential Circuits \u2014 Complete Guide in Easy English<\/p>\r\n <div class=\"hero-pills\">\r\n <span class=\"pill\">\ud83d\udcda 8 Units<\/span>\r\n <span class=\"pill\">\ud83c\udf93 University Level<\/span>\r\n <span class=\"pill\">\u26a1 Circuit Diagrams<\/span>\r\n <span class=\"pill\">\ud83d\udcdd Truth Tables<\/span>\r\n <span class=\"pill\">\ud83d\udd25 Practical Examples<\/span>\r\n <\/div>\r\n<\/section>\r\n\r\n<div class=\"page-wrap\">\r\n\r\n <aside class=\"sidebar\">\r\n <div class=\"sidebar-title\">\ud83d\udccb Course Contents<\/div>\r\n <ul class=\"toc-list\" id=\"toc-nav\">\r\n <li><a href=\"#toc-section\"><span class=\"toc-num\">\ud83d\udccb<\/span> Contents<\/a><\/li>\r\n <li><a href=\"#unit-1\"><span class=\"toc-num\">1<\/span> Number Systems<\/a><\/li>\r\n <li><a href=\"#unit-2\"><span class=\"toc-num\">2<\/span> Boolean Algebra<\/a><\/li>\r\n <li><a href=\"#unit-3\"><span class=\"toc-num\">3<\/span> Logic Gates<\/a><\/li>\r\n <li><a href=\"#unit-4\"><span class=\"toc-num\">4<\/span> Combinational Circuits<\/a><\/li>\r\n <li><a href=\"#unit-5\"><span class=\"toc-num\">5<\/span> Sequential Circuits<\/a><\/li>\r\n <li><a href=\"#unit-6\"><span class=\"toc-num\">6<\/span> Counters & Registers<\/a><\/li>\r\n <li><a href=\"#unit-7\"><span class=\"toc-num\">7<\/span> Memory Systems<\/a><\/li>\r\n <li><a href=\"#unit-8\"><span class=\"toc-num\">8<\/span> Advanced Topics<\/a><\/li>\r\n <\/ul>\r\n <\/aside>\r\n\r\n <main>\r\n\r\n <div id=\"toc-section\">\r\n <div class=\"toc-card-header\"><h2>\ud83d\udccb Table of Contents \u2014 8 Units<\/h2><\/div>\r\n <div class=\"toc-card-body\">\r\n <div class=\"toc-grid\">\r\n <a class=\"toc-item\" href=\"#unit-1\"><span class=\"toc-badge\">1<\/span> Number Systems & Codes<\/a>\r\n <a class=\"toc-item\" href=\"#unit-2\"><span class=\"toc-badge\">2<\/span> Boolean Algebra<\/a>\r\n <a class=\"toc-item\" href=\"#unit-3\"><span class=\"toc-badge\">3<\/span> Logic Gates<\/a>\r\n <a class=\"toc-item\" href=\"#unit-4\"><span class=\"toc-badge\">4<\/span> Combinational Circuits<\/a>\r\n <a class=\"toc-item\" href=\"#unit-5\"><span class=\"toc-badge\">5<\/span> Sequential Circuits<\/a>\r\n <a class=\"toc-item\" href=\"#unit-6\"><span class=\"toc-badge\">6<\/span> Counters & Registers<\/a>\r\n <a class=\"toc-item\" href=\"#unit-7\"><span class=\"toc-badge\">7<\/span> Memory Systems<\/a>\r\n <a class=\"toc-item\" href=\"#unit-8\"><span class=\"toc-badge\">8<\/span> Advanced Topics<\/a>\r\n <\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-1\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 1<\/span>\r\n <h2>Number Systems & Codes<\/h2>\r\n <p>Understanding Binary, Octal, Decimal, Hexadecimal, BCD, Gray Code, ASCII and conversions<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Number System?<\/h3>\r\n <p>A <strong>number system<\/strong> is a mathematical notation for representing numbers using a consistent set of digits or symbols. In digital electronics and computers, different number systems are used to represent data.<\/p>\r\n\r\n <h3>Types of Number Systems<\/h3>\r\n \r\n <table class=\"data-table\">\r\n <thead><tr><th>System<\/th><th>Base<\/th><th>Digits Used<\/th><th>Example<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td><strong>Binary<\/strong><\/td><td>2<\/td><td>0, 1<\/td><td>(1010)\u2082<\/td><\/tr>\r\n <tr><td><strong>Octal<\/strong><\/td><td>8<\/td><td>0-7<\/td><td>(752)\u2088<\/td><\/tr>\r\n <tr><td><strong>Decimal<\/strong><\/td><td>10<\/td><td>0-9<\/td><td>(125)\u2081\u2080<\/td><\/tr>\r\n <tr><td><strong>Hexadecimal<\/strong><\/td><td>16<\/td><td>0-9, A-F<\/td><td>(3A7)\u2081\u2086<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>1. Binary Number System (Base 2)<\/h3>\r\n <p><strong>Binary<\/strong> is the fundamental language of computers and digital circuits. It uses only two digits: <strong>0<\/strong> and <strong>1<\/strong>.<\/p>\r\n\r\n <p><strong>Why Binary?<\/strong><\/p>\r\n <ul>\r\n <li>Digital circuits work with two states: ON (1) and OFF (0)<\/li>\r\n <li>Easy to implement using electronic switches (transistors)<\/li>\r\n <li>High noise immunity (clear distinction between 0 and 1)<\/li>\r\n <li>All data in computers is ultimately stored in binary<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Binary Number Representation<\/span>\r\n\r\nPosition: 7 6 5 4 3 2 1 0\r\nValue: 128 64 32 16 8 4 2 1\r\nBinary: 1 0 1 0 1 1 0 1\r\n\r\n(10101101)\u2082 = 128 + 32 + 8 + 4 + 1 = (173)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>2. Decimal Number System (Base 10)<\/h3>\r\n <p>The standard number system we use in everyday life. Uses digits 0-9.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\nPosition: 3 2 1 0\r\nValue: 1000 100 10 1\r\nDecimal: 5 2 7 3\r\n\r\n(5273)\u2081\u2080 = 5\u00d710\u00b3 + 2\u00d710\u00b2 + 7\u00d710\u00b9 + 3\u00d710\u2070 = 5000 + 200 + 70 + 3\r\n<\/pre><\/div>\r\n\r\n <h3>3. Octal Number System (Base 8)<\/h3>\r\n <p>Uses digits 0-7. Often used as a shorthand for binary (each octal digit = 3 binary bits).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\nPosition: 2 1 0\r\nValue: 64 8 1\r\nOctal: 7 5 2\r\n\r\n(752)\u2088 = 7\u00d78\u00b2 + 5\u00d78\u00b9 + 2\u00d78\u2070 = 448 + 40 + 2 = (490)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>4. Hexadecimal Number System (Base 16)<\/h3>\r\n <p>Uses digits 0-9 and letters A-F (A=10, B=11, C=12, D=13, E=14, F=15). Widely used in programming and memory addressing.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>1<\/td><\/tr>\r\n <tr><td>10<\/td><td>1010<\/td><td>A<\/td><\/tr>\r\n <tr><td>11<\/td><td>1011<\/td><td>B<\/td><\/tr>\r\n <tr><td>12<\/td><td>1100<\/td><td>C<\/td><\/tr>\r\n <tr><td>13<\/td><td>1101<\/td><td>D<\/td><\/tr>\r\n <tr><td>14<\/td><td>1110<\/td><td>E<\/td><\/tr>\r\n <tr><td>15<\/td><td>1111<\/td><td>F<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"code-block\"><pre>\r\n(3A7)\u2081\u2086 = 3\u00d716\u00b2 + 10\u00d716\u00b9 + 7\u00d716\u2070 = 768 + 160 + 7 = (935)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>Number System Conversions<\/h3>\r\n\r\n <p><strong>1. Binary to Decimal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (1101)\u2082 to Decimal<\/span>\r\n\r\n(1101)\u2082 = 1\u00d72\u00b3 + 1\u00d72\u00b2 + 0\u00d72\u00b9 + 1\u00d72\u2070\r\n = 8 + 4 + 0 + 1\r\n = (13)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Decimal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (25)\u2081\u2080 to Binary<\/span>\r\n\r\n25 \u00f7 2 = 12 remainder 1 (LSB)\r\n12 \u00f7 2 = 6 remainder 0\r\n6 \u00f7 2 = 3 remainder 0\r\n3 \u00f7 2 = 1 remainder 1\r\n1 \u00f7 2 = 0 remainder 1 (MSB)\r\n\r\nRead from bottom to top: (11001)\u2082\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. Binary to Octal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Group binary digits in groups of 3 from right to left<\/span>\r\n\r\n(101110101)\u2082 \r\n= 101 110 101\r\n= 5 6 5\r\n= (565)\u2088\r\n<\/pre><\/div>\r\n\r\n <p><strong>4. Binary to Hexadecimal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Group binary digits in groups of 4 from right to left<\/span>\r\n\r\n(10111010)\u2082\r\n= 1011 1010\r\n= B A\r\n= (BA)\u2081\u2086\r\n<\/pre><\/div>\r\n\r\n <p><strong>5. Octal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Convert each octal digit to 3-bit binary<\/span>\r\n\r\n(746)\u2088\r\n7 = 111\r\n4 = 100\r\n6 = 110\r\n= (111100110)\u2082\r\n<\/pre><\/div>\r\n\r\n <p><strong>6. Hexadecimal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Convert each hex digit to 4-bit binary<\/span>\r\n\r\n(2F)\u2081\u2086\r\n2 = 0010\r\nF = 1111\r\n= (00101111)\u2082\r\n<\/pre><\/div>\r\n\r\n <h3>Quick Conversion Table<\/h3>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Octal<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0<\/td><td>0<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>1<\/td><td>1<\/td><\/tr>\r\n <tr><td>2<\/td><td>0010<\/td><td>2<\/td><td>2<\/td><\/tr>\r\n <tr><td>3<\/td><td>0011<\/td><td>3<\/td><td>3<\/td><\/tr>\r\n <tr><td>4<\/td><td>0100<\/td><td>4<\/td><td>4<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>5<\/td><td>5<\/td><\/tr>\r\n <tr><td>6<\/td><td>0110<\/td><td>6<\/td><td>6<\/td><\/tr>\r\n <tr><td>7<\/td><td>0111<\/td><td>7<\/td><td>7<\/td><\/tr>\r\n <tr><td>8<\/td><td>1000<\/td><td>10<\/td><td>8<\/td><\/tr>\r\n <tr><td>9<\/td><td>1001<\/td><td>11<\/td><td>9<\/td><\/tr>\r\n <tr><td>10<\/td><td>1010<\/td><td>12<\/td><td>A<\/td><\/tr>\r\n <tr><td>11<\/td><td>1011<\/td><td>13<\/td><td>B<\/td><\/tr>\r\n <tr><td>12<\/td><td>1100<\/td><td>14<\/td><td>C<\/td><\/tr>\r\n <tr><td>13<\/td><td>1101<\/td><td>15<\/td><td>D<\/td><\/tr>\r\n <tr><td>14<\/td><td>1110<\/td><td>16<\/td><td>E<\/td><\/tr>\r\n <tr><td>15<\/td><td>1111<\/td><td>17<\/td><td>F<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Binary Codes<\/h3>\r\n\r\n <p><strong>1. Binary Coded Decimal (BCD)<\/strong><\/p>\r\n <p>BCD represents each decimal digit (0-9) using 4 binary bits. Also called 8421 code.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (579)\u2081\u2080 to BCD<\/span>\r\n\r\n5 = 0101\r\n7 = 0111\r\n9 = 1001\r\n\r\n(579)\u2081\u2080 = 0101 0111 1001 (BCD)\r\n<\/pre><\/div>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>BCD (8421)<\/th><th>Binary<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0000<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>0001<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>0101<\/td><\/tr>\r\n <tr><td>9<\/td><td>1001<\/td><td>1001<\/td><\/tr>\r\n <tr><td>12<\/td><td>0001 0010<\/td><td>1100<\/td><\/tr>\r\n <tr><td>25<\/td><td>0010 0101<\/td><td>11001<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>BCD vs Pure Binary:<\/strong> BCD uses more bits but makes decimal-to-binary conversion easier for human-readable displays (like calculators and digital clocks).<\/div>\r\n\r\n <p><strong>2. Gray Code (Reflected Binary Code)<\/strong><\/p>\r\n <p>A binary code where two successive values differ by only one bit. Used in rotary encoders, error correction, and analog-to-digital converters.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Gray Code<\/th><th>Bits Changed<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0000<\/td><td>-<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>0001<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>2<\/td><td>0010<\/td><td>0011<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>3<\/td><td>0011<\/td><td>0010<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>4<\/td><td>0100<\/td><td>0110<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>0111<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>6<\/td><td>0110<\/td><td>0101<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>7<\/td><td>0111<\/td><td>0100<\/td><td>1 bit<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Binary to Gray Code Conversion:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Method: MSB stays same, then XOR each adjacent pair<\/span>\r\n\r\nBinary: 1 0 1 1\r\n \u2193 \u2295 \u2295 \u2295\r\nGray: 1 1 1 0\r\n\r\n<span class=\"cm\">Step by step:<\/span>\r\nG\u2083 = B\u2083 = 1\r\nG\u2082 = B\u2083 \u2295 B\u2082 = 1 \u2295 0 = 1\r\nG\u2081 = B\u2082 \u2295 B\u2081 = 0 \u2295 1 = 1\r\nG\u2080 = B\u2081 \u2295 B\u2080 = 1 \u2295 1 = 0\r\n<\/pre><\/div>\r\n\r\n <p><strong>Gray to Binary Conversion:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Method: MSB stays same, then XOR with previous binary bit<\/span>\r\n\r\nGray: 1 1 1 0\r\n \u2193 \u2295 \u2295 \u2295\r\nBinary: 1 0 1 1\r\n\r\n<span class=\"cm\">Step by step:<\/span>\r\nB\u2083 = G\u2083 = 1\r\nB\u2082 = B\u2083 \u2295 G\u2082 = 1 \u2295 1 = 0\r\nB\u2081 = B\u2082 \u2295 G\u2081 = 0 \u2295 1 = 1\r\nB\u2080 = B\u2081 \u2295 G\u2080 = 1 \u2295 0 = 1\r\n<\/pre><\/div>\r\n\r\n <h3>ASCII Code (American Standard Code for Information Interchange)<\/h3>\r\n <p>A 7-bit code (128 characters) used to represent text in computers. Extended ASCII uses 8 bits (256 characters).<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Character<\/th><th>Decimal<\/th><th>Binary<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>A<\/td><td>65<\/td><td>01000001<\/td><td>41<\/td><\/tr>\r\n <tr><td>B<\/td><td>66<\/td><td>01000010<\/td><td>42<\/td><\/tr>\r\n <tr><td>Z<\/td><td>90<\/td><td>01011010<\/td><td>5A<\/td><\/tr>\r\n <tr><td>a<\/td><td>97<\/td><td>01100001<\/td><td>61<\/td><\/tr>\r\n <tr><td>b<\/td><td>98<\/td><td>01100010<\/td><td>62<\/td><\/tr>\r\n <tr><td>0<\/td><td>48<\/td><td>00110000<\/td><td>30<\/td><\/tr>\r\n <tr><td>1<\/td><td>49<\/td><td>00110001<\/td><td>31<\/td><\/tr>\r\n <tr><td>Space<\/td><td>32<\/td><td>00100000<\/td><td>20<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>ASCII Ranges:<\/strong><\/p>\r\n <ul>\r\n <li><strong>0-31:<\/strong> Control characters (non-printable)<\/li>\r\n <li><strong>32-47:<\/strong> Special characters and space<\/li>\r\n <li><strong>48-57:<\/strong> Digits 0-9<\/li>\r\n <li><strong>65-90:<\/strong> Uppercase letters A-Z<\/li>\r\n <li><strong>97-122:<\/strong> Lowercase letters a-z<\/li>\r\n <\/ul>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Quick Tip:<\/strong> To convert uppercase to lowercase in ASCII, add 32. To convert lowercase to uppercase, subtract 32. Example: 'A' (65) + 32 = 'a' (97)<\/div>\r\n\r\n <h3>Signed Number Representation<\/h3>\r\n\r\n <p><strong>1. Sign-Magnitude<\/strong><\/p>\r\n <p>MSB indicates sign (0=positive, 1=negative). Remaining bits represent magnitude.<\/p>\r\n <div class=\"code-block\"><pre>\r\n+5 = 0101 (MSB=0 means positive)\r\n-5 = 1101 (MSB=1 means negative)\r\n\r\n<span class=\"cm\">Problem: Two representations of zero (+0 and -0)<\/span>\r\n+0 = 0000\r\n-0 = 1000\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. 1's Complement<\/strong><\/p>\r\n <p>Positive numbers: normal binary. Negative numbers: invert all bits.<\/p>\r\n <div class=\"code-block\"><pre>\r\n+5 = 0101\r\n-5 = 1010 (invert all bits of +5)\r\n\r\n+7 = 0111\r\n-7 = 1000 (invert all bits of +7)\r\n\r\n<span class=\"cm\">Problem: Still has two zeros<\/span>\r\n+0 = 0000\r\n-0 = 1111\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. 2's Complement (Most Common)<\/strong><\/p>\r\n <p>Positive numbers: normal binary. Negative numbers: invert all bits and add 1.<\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Find 2's complement of +5<\/span>\r\n\r\n+5 = 0101\r\nInvert: 1010\r\nAdd 1: 1011\r\n-5 = 1011\r\n\r\n<span class=\"cm\">Example: Find 2's complement of +7<\/span>\r\n+7 = 0111\r\nInvert: 1000\r\nAdd 1: 1001\r\n-7 = 1001\r\n\r\n<span class=\"cm\">Advantage: Only one representation of zero<\/span>\r\n+0 = 0000\r\n<\/pre><\/div>\r\n\r\n <p><strong>2's Complement Range for n bits:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Range:<\/strong> -2<sup>n-1<\/sup> to +2<sup>n-1<\/sup>-1<\/li>\r\n <li><strong>4-bit:<\/strong> -8 to +7<\/li>\r\n <li><strong>8-bit:<\/strong> -128 to +127<\/li>\r\n <li><strong>16-bit:<\/strong> -32,768 to +32,767<\/li>\r\n <\/ul>\r\n\r\n <h3>Binary Arithmetic<\/h3>\r\n\r\n <p><strong>Binary Addition Rules:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 0 + 0 = 0\r\n 0 + 1 = 1\r\n 1 + 0 = 1\r\n 1 + 1 = 10 (0 with carry 1)\r\n1 + 1 + 1 = 11 (1 with carry 1)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: 1011 + 1101<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n \u2081\u2081\u2081 (carries)\r\n 1011 (11 in decimal)\r\n + 1101 (13 in decimal)\r\n ------\r\n 11000 (24 in decimal)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Binary Subtraction Rules:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 0 - 0 = 0\r\n 1 - 0 = 1\r\n 1 - 1 = 0\r\n 0 - 1 = 1 (with borrow 1)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: 1101 - 1011<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 1101 (13 in decimal)\r\n - 1011 (11 in decimal)\r\n ------\r\n 0010 (2 in decimal)\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Convert (11010110)\u2082 to Decimal, Octal, and Hexadecimal. 2) Convert (456)\u2081\u2080 to Binary, Octal, and Hexadecimal. 3) Convert (3F7)\u2081\u2086 to Binary. 4) Find 2's complement of (01101)\u2082. 5) Add (1011)\u2082 + (1110)\u2082<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-2\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 2<\/span>\r\n <h2>Boolean Algebra<\/h2>\r\n <p>Laws, theorems, De Morgan's rules, simplification techniques and truth tables<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is Boolean Algebra?<\/h3>\r\n <p><strong>Boolean Algebra<\/strong> is a branch of algebra that deals with binary variables and logical operations. Developed by <strong>George Boole<\/strong> in 1854, it forms the foundation of digital logic design.<\/p>\r\n\r\n <p><strong>Boolean Variables:<\/strong> Can have only two values: <strong>0 (False)<\/strong> or <strong>1 (True)<\/strong><\/p>\r\n\r\n <h3>Basic Boolean Operations<\/h3>\r\n\r\n <p><strong>1. AND Operation (\u00b7)<\/strong><\/p>\r\n <p>Output is 1 only when ALL inputs are 1. Symbol: \u00b7 or \u2227<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A \u00b7 B or Z = A AND B or Z = AB\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Z=A\u00b7B\r\n0 0 | 0\r\n0 1 | 0\r\n1 0 | 0\r\n1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. OR Operation (+)<\/strong><\/p>\r\n <p>Output is 1 when AT LEAST ONE input is 1. Symbol: + or \u2228<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A + B or Z = A OR B\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Z=A+B\r\n0 0 | 0\r\n0 1 | 1\r\n1 0 | 1\r\n1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. NOT Operation (')<\/strong><\/p>\r\n <p>Output is the complement\/inverse of input. Symbol: ' or \u00ac or \u203e<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A' or Z = NOT A or Z = \u0100\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA | Z=A'\r\n0 | 1\r\n1 | 0\r\n<\/pre><\/div>\r\n\r\n <h3>Boolean Algebra Laws<\/h3>\r\n\r\n <p><strong>1. Identity Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Identity<\/div>\r\n <div class=\"concept-rule\">A + 0 = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Identity<\/div>\r\n <div class=\"concept-rule\">A \u00b7 1 = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>2. Null (Dominance) Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Null<\/div>\r\n <div class=\"concept-rule\">A + 1 = 1<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Null<\/div>\r\n <div class=\"concept-rule\">A \u00b7 0 = 0<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>3. Idempotent Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Idempotent<\/div>\r\n <div class=\"concept-rule\">A + A = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Idempotent<\/div>\r\n <div class=\"concept-rule\">A \u00b7 A = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>4. Complement Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Complement<\/div>\r\n <div class=\"concept-rule\">A + A' = 1<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Complement<\/div>\r\n <div class=\"concept-rule\">A \u00b7 A' = 0<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Double Negation<\/div>\r\n <div class=\"concept-rule\">(A')' = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>5. Commutative Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Commutative<\/div>\r\n <div class=\"concept-rule\">A + B = B + A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Commutative<\/div>\r\n <div class=\"concept-rule\">A \u00b7 B = B \u00b7 A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>6. Associative Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Associative<\/div>\r\n <div class=\"concept-rule\">A+(B+C) = (A+B)+C<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Associative<\/div>\r\n <div class=\"concept-rule\">A\u00b7(B\u00b7C) = (A\u00b7B)\u00b7C<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>7. Distributive Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND over OR<\/div>\r\n <div class=\"concept-rule\">A\u00b7(B+C) = A\u00b7B + A\u00b7C<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR over AND<\/div>\r\n <div class=\"concept-rule\">A+(B\u00b7C) = (A+B)\u00b7(A+C)<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>8. Absorption Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 1<\/div>\r\n <div class=\"concept-rule\">A + A\u00b7B = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 2<\/div>\r\n <div class=\"concept-rule\">A \u00b7 (A+B) = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 3<\/div>\r\n <div class=\"concept-rule\">A + A'\u00b7B = A + B<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 4<\/div>\r\n <div class=\"concept-rule\">A \u00b7 (A'+B) = A \u00b7 B<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <h3>De Morgan's Theorems<\/h3>\r\n <p><strong>De Morgan's Laws<\/strong> are fundamental theorems for complementing Boolean expressions:<\/p>\r\n\r\n <p><strong>Theorem 1:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A + B)' = A' \u00b7 B'\r\n\r\n<span class=\"cm\">The complement of OR equals AND of complements<\/span>\r\n\r\n<span class=\"cm\">Proof by Truth Table:<\/span>\r\nA B | A+B (A+B)' | A' B' A'\u00b7B'\r\n0 0 | 0 1 | 1 1 1 \u2713\r\n0 1 | 1 0 | 1 0 0 \u2713\r\n1 0 | 1 0 | 0 1 0 \u2713\r\n1 1 | 1 0 | 0 0 0 \u2713\r\n<\/pre><\/div>\r\n\r\n <p><strong>Theorem 2:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A \u00b7 B)' = A' + B'\r\n\r\n<span class=\"cm\">The complement of AND equals OR of complements<\/span>\r\n\r\n<span class=\"cm\">Proof by Truth Table:<\/span>\r\nA B | A\u00b7B (A\u00b7B)' | A' B' A'+B'\r\n0 0 | 0 1 | 1 1 1 \u2713\r\n0 1 | 0 1 | 1 0 1 \u2713\r\n1 0 | 0 1 | 0 1 1 \u2713\r\n1 1 | 1 0 | 0 0 0 \u2713\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>De Morgan's Quick Rule:<\/strong> Break the bar, change the operation (+ to \u00b7, or \u00b7 to +)<\/div>\r\n\r\n <p><strong>Extended De Morgan's:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A + B + C)' = A' \u00b7 B' \u00b7 C'\r\n\r\n(A \u00b7 B \u00b7 C)' = A' + B' + C'\r\n\r\n(A + B\u00b7C)' = A' \u00b7 (B'+C')\r\n\r\n(A\u00b7B + C\u00b7D)' = (A'+B') \u00b7 (C'+D')\r\n<\/pre><\/div>\r\n\r\n <h3>Boolean Expression Simplification<\/h3>\r\n\r\n <p><strong>Example 1: Simplify A\u00b7B + A\u00b7B'<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA\u00b7B + A\u00b7B'\r\n= A\u00b7(B + B') <span class=\"cm\">Distributive law<\/span>\r\n= A\u00b71 <span class=\"cm\">Complement law: B+B'=1<\/span>\r\n= A <span class=\"cm\">Identity law: A\u00b71=A<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 2: Simplify (A+B)\u00b7(A+B')<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A+B)\u00b7(A+B')\r\n= A + B\u00b7B' <span class=\"cm\">Distributive law<\/span>\r\n= A + 0 <span class=\"cm\">Complement law: B\u00b7B'=0<\/span>\r\n= A <span class=\"cm\">Identity law: A+0=A<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 3: Simplify A + A\u00b7B<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA + A\u00b7B\r\n= A\u00b71 + A\u00b7B <span class=\"cm\">Identity law: A=A\u00b71<\/span>\r\n= A\u00b7(1 + B) <span class=\"cm\">Distributive law<\/span>\r\n= A\u00b71 <span class=\"cm\">Null law: 1+B=1<\/span>\r\n= A <span class=\"cm\">Identity law<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 4: Simplify A'\u00b7B\u00b7C + A\u00b7B\u00b7C + A\u00b7B\u00b7C'<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA'\u00b7B\u00b7C + A\u00b7B\u00b7C + A\u00b7B\u00b7C'\r\n= B\u00b7C\u00b7(A'+A) + A\u00b7B\u00b7C' <span class=\"cm\">Factor out B\u00b7C<\/span>\r\n= B\u00b7C\u00b71 + A\u00b7B\u00b7C' <span class=\"cm\">Complement law<\/span>\r\n= B\u00b7C + A\u00b7B\u00b7C' <span class=\"cm\">Identity law<\/span>\r\n= B\u00b7(C + A\u00b7C') <span class=\"cm\">Factor out B<\/span>\r\n= B\u00b7(C + A) <span class=\"cm\">Absorption law<\/span>\r\n= A\u00b7B + B\u00b7C <span class=\"cm\">Distributive law<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Standard Forms of Boolean Expressions<\/h3>\r\n\r\n <p><strong>1. Sum of Products (SOP)<\/strong><\/p>\r\n <p>OR of AND terms. Each AND term is called a <strong>minterm<\/strong>.<\/p>\r\n <div class=\"code-block\"><pre>\r\nF = A'\u00b7B\u00b7C + A\u00b7B'\u00b7C + A\u00b7B\u00b7C'\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,7)<\/span>\r\nF = A'\u00b7B'\u00b7C + A'\u00b7B\u00b7C + A\u00b7B'\u00b7C + A\u00b7B\u00b7C\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Product of Sums (POS)<\/strong><\/p>\r\n <p>AND of OR terms. Each OR term is called a <strong>maxterm<\/strong>.<\/p>\r\n <div class=\"code-block\"><pre>\r\nF = (A+B+C)\u00b7(A+B'+C)\u00b7(A'+B+C')\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a0M(0,2,4,6)<\/span>\r\nF = (A+B+C)\u00b7(A+B+C')\u00b7(A+B'+C)\u00b7(A+B'+C')\r\n<\/pre><\/div>\r\n\r\n <h3>Truth Table to Boolean Expression<\/h3>\r\n\r\n <p><strong>Example: Create expression from truth table<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B C | F\r\n0 0 0 | 0\r\n0 0 1 | 1 \u2190 m\u2081 = A'\u00b7B'\u00b7C\r\n0 1 0 | 0\r\n0 1 1 | 1 \u2190 m\u2083 = A'\u00b7B\u00b7C\r\n1 0 0 | 1 \u2190 m\u2084 = A\u00b7B'\u00b7C'\r\n1 0 1 | 0\r\n1 1 0 | 1 \u2190 m\u2086 = A\u00b7B\u00b7C'\r\n1 1 1 | 0\r\n\r\n<span class=\"cm\">SOP Form (use rows where F=1):<\/span>\r\nF = A'\u00b7B'\u00b7C + A'\u00b7B\u00b7C + A\u00b7B'\u00b7C' + A\u00b7B\u00b7C'\r\n\r\n<span class=\"cm\">Simplified:<\/span>\r\nF = A'\u00b7C\u00b7(B'+B) + A\u00b7C'\u00b7(B'+B)\r\nF = A'\u00b7C + A\u00b7C'\r\n<\/pre><\/div>\r\n\r\n <h3>Canonical Forms<\/h3>\r\n\r\n <p><strong>Minterms (m):<\/strong> Product terms with all variables present (in normal or complement form)<\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Row<\/th><th>A B C<\/th><th>Minterm<\/th><th>Notation<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0 0 0<\/td><td>A'\u00b7B'\u00b7C'<\/td><td>m\u2080<\/td><\/tr>\r\n <tr><td>1<\/td><td>0 0 1<\/td><td>A'\u00b7B'\u00b7C<\/td><td>m\u2081<\/td><\/tr>\r\n <tr><td>2<\/td><td>0 1 0<\/td><td>A'\u00b7B\u00b7C'<\/td><td>m\u2082<\/td><\/tr>\r\n <tr><td>3<\/td><td>0 1 1<\/td><td>A'\u00b7B\u00b7C<\/td><td>m\u2083<\/td><\/tr>\r\n <tr><td>4<\/td><td>1 0 0<\/td><td>A\u00b7B'\u00b7C'<\/td><td>m\u2084<\/td><\/tr>\r\n <tr><td>5<\/td><td>1 0 1<\/td><td>A\u00b7B'\u00b7C<\/td><td>m\u2085<\/td><\/tr>\r\n <tr><td>6<\/td><td>1 1 0<\/td><td>A\u00b7B\u00b7C'<\/td><td>m\u2086<\/td><\/tr>\r\n <tr><td>7<\/td><td>1 1 1<\/td><td>A\u00b7B\u00b7C<\/td><td>m\u2087<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Maxterms (M):<\/strong> Sum terms with all variables present<\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Row<\/th><th>A B C<\/th><th>Maxterm<\/th><th>Notation<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0 0 0<\/td><td>A+B+C<\/td><td>M\u2080<\/td><\/tr>\r\n <tr><td>1<\/td><td>0 0 1<\/td><td>A+B+C'<\/td><td>M\u2081<\/td><\/tr>\r\n <tr><td>2<\/td><td>0 1 0<\/td><td>A+B'+C<\/td><td>M\u2082<\/td><\/tr>\r\n <tr><td>3<\/td><td>0 1 1<\/td><td>A+B'+C'<\/td><td>M\u2083<\/td><\/tr>\r\n <tr><td>4<\/td><td>1 0 0<\/td><td>A'+B+C<\/td><td>M\u2084<\/td><\/tr>\r\n <tr><td>5<\/td><td>1 0 1<\/td><td>A'+B+C'<\/td><td>M\u2085<\/td><\/tr>\r\n <tr><td>6<\/td><td>1 1 0<\/td><td>A'+B'+C<\/td><td>M\u2086<\/td><\/tr>\r\n <tr><td>7<\/td><td>1 1 1<\/td><td>A'+B'+C'<\/td><td>M\u2087<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Quick Conversion:<\/strong> SOP to POS: F(A,B,C) = \u03a3m(1,3,5,7) = \u03a0M(0,2,4,6). Use rows NOT in minterm list for maxterm list.<\/div>\r\n\r\n <h3>Consensus Theorem<\/h3>\r\n <div class=\"code-block\"><pre>\r\nA\u00b7B + A'\u00b7C + B\u00b7C = A\u00b7B + A'\u00b7C\r\n\r\n<span class=\"cm\">The term B\u00b7C is redundant (consensus term)<\/span>\r\n\r\n<span class=\"cm\">Dual form:<\/span>\r\n(A+B)\u00b7(A'+C)\u00b7(B+C) = (A+B)\u00b7(A'+C)\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Simplify: A\u00b7B + A'\u00b7C + B\u00b7C 2) Apply De Morgan's: (A+B\u00b7C)' 3) Convert to SOP: F(A,B,C) with F=1 for rows 1,2,4,7 4) Prove: A+A\u00b7B = A using Boolean laws 5) Simplify: (A+B)\u00b7(A'+B)\u00b7(A+B')<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-3\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 3<\/span>\r\n <h2>Logic Gates<\/h2>\r\n <p>AND, OR, NOT, NAND, NOR, XOR, XNOR gates with symbols, truth tables, and diagrams<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Logic Gate?<\/h3>\r\n <p>A <strong>logic gate<\/strong> is a basic building block of digital circuits. It performs a logical operation on one or more binary inputs and produces a single binary output.<\/p>\r\n\r\n <div class=\"feature-grid\">\r\n <div class=\"feature-item\">\ud83d\udd0c Basic Gates: AND, OR, NOT<\/div>\r\n <div class=\"feature-item\">\u26a1 Universal Gates: NAND, NOR<\/div>\r\n <div class=\"feature-item\">\ud83d\udd04 Special Gates: XOR, XNOR<\/div>\r\n <div class=\"feature-item\">\ud83d\udca1 Used in CPUs, Memory, ALUs<\/div>\r\n <\/div>\r\n\r\n <h3>1. AND Gate<\/h3>\r\n <p>Output is HIGH (1) only when ALL inputs are HIGH.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502\u2572\r\n \u2502 \u2572\r\n \u2502 \u251c\u2500\u2500\u2500 Y = A\u00b7B\r\n \u2502 \u2571\r\n \u2502\u2571\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A \u00b7 B or Y = AB\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A\u00b7B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Enable\/disable signals, multiplication in ALU, conditional operations<\/p>\r\n\r\n <h3>2. OR Gate<\/h3>\r\n <p>Output is HIGH when AT LEAST ONE input is HIGH.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502)\r\n \u2502 )\r\n \u2502 \u251c\u2500\u2500\u2500 Y = A+B\r\n \u2502 )\r\n \u2502)\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A + B\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A+B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Combining multiple enable signals, addition in ALU, error detection<\/p>\r\n\r\n <h3>3. NOT Gate (Inverter)<\/h3>\r\n <p>Output is the inverse of input. Single input gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u25b7\u25cb\u2500\u2500\u2500 Y = A'\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A' or Y = \u0100\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 Y=A' \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Inverting signals, creating complement, clock signal inversion<\/p>\r\n\r\n <h3>4. NAND Gate (NOT-AND)<\/h3>\r\n <p>Output is LOW only when ALL inputs are HIGH. Complement of AND gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502\u2572\r\n \u2502 \u2572\r\n \u2502 \u251c\u25cb\u2500\u2500\u2500 Y = (A\u00b7B)'\r\n \u2502 \u2571\r\n \u2502\u2571\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A \u00b7 B)' or Y = A\u0305\u00b7\u0305B\u0305\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A\u00b7B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Universal Gate:<\/strong> NAND gate can implement ANY logic function (AND, OR, NOT, etc.). It's the most commonly used gate in IC fabrication.<\/div>\r\n\r\n <h3>5. NOR Gate (NOT-OR)<\/h3>\r\n <p>Output is HIGH only when ALL inputs are LOW. Complement of OR gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502)\r\n \u2502 )\r\n \u2502 \u251c\u25cb\u2500\u2500\u2500 Y = (A+B)'\r\n \u2502 )\r\n \u2502)\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A + B)' or Y = A\u0305+\u0305B\u0305\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A+B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Universal Gate:<\/strong> NOR gate can also implement ANY logic function. Both NAND and NOR are universal gates.<\/div>\r\n\r\n <h3>6. XOR Gate (Exclusive-OR)<\/h3>\r\n <p>Output is HIGH when inputs are DIFFERENT.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n ))\r\n ) )\r\n ) \u251c\u2500\u2500\u2500 Y = A\u2295B\r\n ) )\r\n ))\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A \u2295 B = A'\u00b7B + A\u00b7B'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A\u2295B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Addition circuits (Half Adder, Full Adder), parity checkers, data encryption<\/p>\r\n\r\n <h3>7. XNOR Gate (Exclusive-NOR)<\/h3>\r\n <p>Output is HIGH when inputs are SAME. Complement of XOR.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n ))\r\n ) )\r\n ) \u251c\u25cb\u2500\u2500\u2500 Y = (A\u2295B)'\r\n ) )\r\n ))\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A \u2295 B)' = A\u00b7B + A'\u00b7B'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A\u2295B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Equality checker, comparators, error detection<\/p>\r\n\r\n <h3>Summary of All Gates<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Gate<\/th><th>Expression<\/th><th>Output 1 when<\/th><th>Type<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>AND<\/td><td>A\u00b7B<\/td><td>ALL inputs are 1<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>OR<\/td><td>A+B<\/td><td>AT LEAST ONE input is 1<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>NOT<\/td><td>A'<\/td><td>Input is 0<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>NAND<\/td><td>(A\u00b7B)'<\/td><td>AT LEAST ONE input is 0<\/td><td>Universal<\/td><\/tr>\r\n <tr><td>NOR<\/td><td>(A+B)'<\/td><td>ALL inputs are 0<\/td><td>Universal<\/td><\/tr>\r\n <tr><td>XOR<\/td><td>A\u2295B<\/td><td>Inputs are DIFFERENT<\/td><td>Special<\/td><\/tr>\r\n <tr><td>XNOR<\/td><td>(A\u2295B)'<\/td><td>Inputs are SAME<\/td><td>Special<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Complete Truth Table Comparison<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 AND \u2502 OR \u2502 NOT \u2502 NAND \u2502 NOR \u2502 XOR \u2502 XNOR \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502 0 \u2502 1,0 \u2502 1 \u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502 1 \u2502 1,0 \u2502 1 \u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502 1 \u2502 0,1 \u2502 1 \u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502 1 \u2502 0,1 \u2502 0 \u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Implementing Gates Using NAND<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. NOT using NAND:<\/span>\r\n A \u2500\u2500\u2500\u2500NAND\u2500\u2500\u2500\u2500 A' (Connect both inputs together)\r\n \u2502\r\n A \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">2. AND using NAND:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n NAND\u2500\u2500NAND\u2500\u2500 A\u00b7B\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">3. OR using NAND:<\/span>\r\n A \u2500\u2500NAND\u2500\u2500\u2510\r\n NAND\u2500\u2500 A+B\r\n B \u2500\u2500NAND\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">4. NOR using NAND:<\/span>\r\n A \u2500\u2500NAND\u2500\u2500\u2510\r\n NAND\u2500\u2500NAND\u2500\u2500 (A+B)'\r\n B \u2500\u2500NAND\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Implementing Gates Using NOR<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. NOT using NOR:<\/span>\r\n A \u2500\u2500\u2500\u2500NOR\u2500\u2500\u2500\u2500 A' (Connect both inputs together)\r\n \u2502\r\n A \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">2. OR using NOR:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n NOR\u2500\u2500NOR\u2500\u2500 A+B\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">3. AND using NOR:<\/span>\r\n A \u2500\u2500NOR\u2500\u2500\u2510\r\n NOR\u2500\u2500 A\u00b7B\r\n B \u2500\u2500NOR\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">4. NAND using NOR:<\/span>\r\n A \u2500\u2500NOR\u2500\u2500\u2510\r\n NOR\u2500\u2500NOR\u2500\u2500 (A\u00b7B)'\r\n B \u2500\u2500NOR\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Multiple-Input Gates<\/h3>\r\n\r\n <p><strong>3-Input AND Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A\u00b7B\u00b7C<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0\r\n0 0 1 | 0\r\n0 1 0 | 0\r\n0 1 1 | 0\r\n1 0 0 | 0\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1 \u2190 Only when ALL are 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Input OR Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A+B+C<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0 \u2190 Only when ALL are 0\r\n0 0 1 | 1\r\n0 1 0 | 1\r\n0 1 1 | 1\r\n1 0 0 | 1\r\n1 0 1 | 1\r\n1 1 0 | 1\r\n1 1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Input XOR Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A\u2295B\u2295C (Output 1 when ODD number of 1s)<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0\r\n0 0 1 | 1 \u2190 Odd (1)\r\n0 1 0 | 1 \u2190 Odd (1)\r\n0 1 1 | 0\r\n1 0 0 | 1 \u2190 Odd (1)\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1 \u2190 Odd (3)\r\n<\/pre><\/div>\r\n\r\n <h3>Tri-State Buffer<\/h3>\r\n <p>A special gate with 3 output states: HIGH (1), LOW (0), and HIGH-IMPEDANCE (Z - disconnected).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n Data \u2500\u2500\u2500\u2500\u25b7\u2500\u2500\u2500\u2500 Output\r\n \u2502\r\n Enable\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEnable Data | Output\r\n 0 X | Z (High-impedance, disconnected)\r\n 1 0 | 0\r\n 1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Bus systems, memory interfacing, bidirectional data lines<\/p>\r\n\r\n <h3>Logic Gate IC Packages<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Gate Type<\/th><th>Description<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>7400<\/td><td>NAND<\/td><td>Quad 2-input NAND gates<\/td><\/tr>\r\n <tr><td>7402<\/td><td>NOR<\/td><td>Quad 2-input NOR gates<\/td><\/tr>\r\n <tr><td>7404<\/td><td>NOT<\/td><td>Hex inverters<\/td><\/tr>\r\n <tr><td>7408<\/td><td>AND<\/td><td>Quad 2-input AND gates<\/td><\/tr>\r\n <tr><td>7432<\/td><td>OR<\/td><td>Quad 2-input OR gates<\/td><\/tr>\r\n <tr><td>7486<\/td><td>XOR<\/td><td>Quad 2-input XOR gates<\/td><\/tr>\r\n <tr><td>74266<\/td><td>XNOR<\/td><td>Quad 2-input XNOR gates<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Draw logic circuit for: Y = A\u00b7B + B\u00b7C' 2) Create truth table for 3-input NAND gate 3) Implement OR gate using only NAND gates 4) Find output of XOR gate when A=1, B=0 5) What is the output of: (A NAND B) OR (C XOR D) for A=1, B=1, C=0, D=1?<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-4\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 4<\/span>\r\n <h2>Combinational Circuits<\/h2>\r\n <p>Adders, Subtractors, Multiplexers, Demultiplexers, Encoders, Decoders, Comparators<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What are Combinational Circuits?<\/h3>\r\n <p><strong>Combinational circuits<\/strong> are logic circuits whose outputs depend ONLY on present inputs (no memory). Output changes immediately when input changes.<\/p>\r\n\r\n <p><strong>Characteristics:<\/strong><\/p>\r\n <ul>\r\n <li>No feedback loops<\/li>\r\n <li>No memory elements (no flip-flops)<\/li>\r\n <li>Output = f(present inputs only)<\/li>\r\n <li>Faster than sequential circuits<\/li>\r\n <\/ul>\r\n\r\n <h3>1. Half Adder<\/h3>\r\n <p>Adds two 1-bit binary numbers. Produces SUM and CARRY.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Sum Carry\r\n0 0 | 0 0\r\n0 1 | 1 0\r\n1 0 | 1 0\r\n1 1 | 0 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nSum = A \u2295 B (XOR)\r\nCarry = A \u00b7 B (AND)\r\n\r\n<span class=\"cm\">Circuit Diagram:<\/span>\r\nA \u2500\u2500\u2500\u2510\r\n XOR\u2500\u2500\u2500\u2500 Sum\r\nB \u2500\u2500\u2500\u2518\r\n\r\nA \u2500\u2500\u2500\u2510\r\n AND\u2500\u2500\u2500\u2500 Carry\r\nB \u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>2. Full Adder<\/h3>\r\n <p>Adds THREE 1-bit binary numbers (A, B, and Carry-in). Produces SUM and CARRY-out.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B Cin | Sum Cout\r\n0 0 0 | 0 0\r\n0 0 1 | 1 0\r\n0 1 0 | 1 0\r\n0 1 1 | 0 1\r\n1 0 0 | 1 0\r\n1 0 1 | 0 1\r\n1 1 0 | 0 1\r\n1 1 1 | 1 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nSum = A \u2295 B \u2295 Cin\r\nCout = A\u00b7B + Cin\u00b7(A\u2295B)\r\n = A\u00b7B + B\u00b7Cin + A\u00b7Cin\r\n\r\n<span class=\"cm\">Implementation using Two Half Adders:<\/span>\r\nA \u2500\u2500\u2510 \u250c\u2500\u2500\u2500 Sum\r\n HA1 \u2500\u2500 S \u2500\u2500\u2500HA2\r\nB \u2500\u2500\u2518 C \u2502\r\n \u2502 Cin\r\n \u2514\u2500\u2500OR\u2500\u2500\u2518\u2500\u2500\u2500 Cout\r\n<\/pre><\/div>\r\n\r\n <h3>4-bit Binary Adder (Ripple Carry)<\/h3>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Connects 4 Full Adders in series<\/span>\r\n\r\nA\u2083B\u2083 A\u2082B\u2082 A\u2081B\u2081 A\u2080B\u2080\r\n \u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502\r\n FA FA FA FA\r\n \u2502 \u2502 \u2502 \u2502\r\nC\u2084\u2500\u2500\u2500\u2500C\u2083\u2500\u2500\u2500\u2500C\u2082\u2500\u2500\u2500\u2500C\u2081\u2500\u2500\u2500\u2500C\u2080(0)\r\n\r\nSum: S\u2083 S\u2082 S\u2081 S\u2080\r\nCarry: C\u2084\r\n<\/pre><\/div>\r\n\r\n <h3>3. Half Subtractor<\/h3>\r\n <p>Subtracts two 1-bit binary numbers.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Diff Borrow\r\n0 0 | 0 0\r\n0 1 | 1 1\r\n1 0 | 1 0\r\n1 1 | 0 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nDiff = A \u2295 B\r\nBorrow = A'\u00b7B\r\n<\/pre><\/div>\r\n\r\n <h3>4. Full Subtractor<\/h3>\r\n <p>Subtracts three bits (A - B - Bin).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nDiff = A \u2295 B \u2295 Bin\r\nBout = A'\u00b7B + Bin\u00b7(A\u2295B)'\r\n = A'\u00b7B + A'\u00b7Bin + B\u00b7Bin\r\n<\/pre><\/div>\r\n\r\n <h3>5. Multiplexer (MUX)<\/h3>\r\n <p>Data selector. Selects ONE of many inputs and forwards it to output based on select lines.<\/p>\r\n\r\n <p><strong>2:1 Multiplexer (2 inputs, 1 select line)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nI\u2080 \u2500\u2500\u2510\r\n \u2502 MUX\r\nI\u2081 \u2500\u2500\u2524 2:1 \u2500\u2500\u2500\u2500 Y\r\n \u2502\r\nS \u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS | Y\r\n0 | I\u2080\r\n1 | I\u2081\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span>\r\nY = S'\u00b7I\u2080 + S\u00b7I\u2081\r\n<\/pre><\/div>\r\n\r\n <p><strong>4:1 Multiplexer (4 inputs, 2 select lines)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nI\u2080 \u2500\u2500\u2510\r\nI\u2081 \u2500\u2500\u2524 MUX\r\nI\u2082 \u2500\u2500\u2524 4:1 \u2500\u2500\u2500\u2500 Y\r\nI\u2083 \u2500\u2500\u2518\r\nS\u2081S\u2080\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS\u2081 S\u2080 | Y\r\n0 0 | I\u2080\r\n0 1 | I\u2081\r\n1 0 | I\u2082\r\n1 1 | I\u2083\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span>\r\nY = S\u2081'\u00b7S\u2080'\u00b7I\u2080 + S\u2081'\u00b7S\u2080\u00b7I\u2081 + S\u2081\u00b7S\u2080'\u00b7I\u2082 + S\u2081\u00b7S\u2080\u00b7I\u2083\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Data routing, parallel-to-serial conversion, function generators, ALU input selection<\/p>\r\n\r\n <h3>6. Demultiplexer (DEMUX)<\/h3>\r\n <p>Data distributor. Routes ONE input to ONE of many outputs based on select lines.<\/p>\r\n\r\n <p><strong>1:4 Demultiplexer<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\n \u250c\u2500\u2500\u2500\u2500 Y\u2080\r\n \u2502\r\n D\u2500\u2500\u2500\u2500\u2524DEMUX Y\u2081\r\n 1:4 \u2502\r\n \u2502\u2500\u2500\u2500\u2500 Y\u2082\r\n \u2502\r\n \u2514\u2500\u2500\u2500\u2500 Y\u2083\r\n S\u2081S\u2080\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS\u2081 S\u2080 | Y\u2080 Y\u2081 Y\u2082 Y\u2083\r\n0 0 | D 0 0 0\r\n0 1 | 0 D 0 0\r\n1 0 | 0 0 D 0\r\n1 1 | 0 0 0 D\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2080 = S\u2081'\u00b7S\u2080'\u00b7D\r\nY\u2081 = S\u2081'\u00b7S\u2080\u00b7D\r\nY\u2082 = S\u2081\u00b7S\u2080'\u00b7D\r\nY\u2083 = S\u2081\u00b7S\u2080\u00b7D\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Serial-to-parallel conversion, address decoding, communication systems<\/p>\r\n\r\n <h3>7. Encoder<\/h3>\r\n <p>Converts 2\u207f input lines to n output lines. Only ONE input should be active at a time.<\/p>\r\n\r\n <p><strong>4:2 Encoder (4 inputs to 2 outputs)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nI\u2083 I\u2082 I\u2081 I\u2080 | Y\u2081 Y\u2080\r\n0 0 0 1 | 0 0\r\n0 0 1 0 | 0 1\r\n0 1 0 0 | 1 0\r\n1 0 0 0 | 1 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2081 = I\u2083 + I\u2082\r\nY\u2080 = I\u2083 + I\u2081\r\n<\/pre><\/div>\r\n\r\n <p><strong>Priority Encoder:<\/strong> When multiple inputs are active, encodes the highest priority input.<\/p>\r\n\r\n <p><strong>Applications:<\/strong> Keyboard encoding, interrupt handling, data compression<\/p>\r\n\r\n <h3>8. Decoder<\/h3>\r\n <p>Converts n input lines to 2\u207f output lines. Only ONE output is active for each input combination.<\/p>\r\n\r\n <p><strong>2:4 Decoder (2 inputs to 4 outputs)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA\u2081 A\u2080 | Y\u2083 Y\u2082 Y\u2081 Y\u2080\r\n0 0 | 0 0 0 1\r\n0 1 | 0 0 1 0\r\n1 0 | 0 1 0 0\r\n1 1 | 1 0 0 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2080 = A\u2081'\u00b7A\u2080'\r\nY\u2081 = A\u2081'\u00b7A\u2080\r\nY\u2082 = A\u2081\u00b7A\u2080'\r\nY\u2083 = A\u2081\u00b7A\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Memory address decoding, instruction decoding, display drivers (7-segment)<\/p>\r\n\r\n <h3>9. 7-Segment Display Decoder<\/h3>\r\n <p>Converts 4-bit BCD to 7-segment display output.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">7-Segment Display Layout:<\/span>\r\n aaa\r\n f b\r\n ggg\r\n e c\r\n ddd\r\n\r\n<span class=\"cm\">BCD to 7-Segment:<\/span>\r\nBCD | abcdefg | Display\r\n0000 | 1111110 | 0\r\n0001 | 0110000 | 1\r\n0010 | 1101101 | 2\r\n0011 | 1111001 | 3\r\n0100 | 0110011 | 4\r\n0101 | 1011011 | 5\r\n0110 | 1011111 | 6\r\n0111 | 1110000 | 7\r\n1000 | 1111111 | 8\r\n1001 | 1111011 | 9\r\n<\/pre><\/div>\r\n\r\n <h3>10. Magnitude Comparator<\/h3>\r\n <p>Compares two binary numbers and indicates whether they are equal, or one is greater\/less than the other.<\/p>\r\n\r\n <p><strong>1-bit Comparator:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | A>B A=B A<B\r\n0 0 | 0 1 0\r\n0 1 | 0 0 1\r\n1 0 | 1 0 0\r\n1 1 | 0 1 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nA > B = A\u00b7B'\r\nA = B = A'\u00b7B' + A\u00b7B = (A\u2295B)'\r\nA < B = A'\u00b7B\r\n<\/pre><\/div>\r\n\r\n <p><strong>2-bit Comparator:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Compare A\u2081A\u2080 with B\u2081B\u2080<\/span>\r\n\r\nA=B when: (A\u2081\u2295B\u2081)' \u00b7 (A\u2080\u2295B\u2080)'\r\n\r\nA>B when: A\u2081\u00b7B\u2081' + (A\u2081\u2295B\u2081)'\u00b7A\u2080\u00b7B\u2080'\r\n\r\nA<B when: A\u2081'\u00b7B\u2081 + (A\u2081\u2295B\u2081)'\u00b7A\u2080'\u00b7B\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Sorting algorithms, control circuits, microprocessor ALU<\/p>\r\n\r\n <h3>Combinational Circuit Design Steps<\/h3>\r\n\r\n <p><strong>Step-by-step Design Process:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Step 1:<\/strong> Problem Statement - Understand what the circuit should do<\/li>\r\n <li><strong>Step 2:<\/strong> Input\/Output Identification - Determine number and type of I\/O<\/li>\r\n <li><strong>Step 3:<\/strong> Truth Table - List all input combinations and desired outputs<\/li>\r\n <li><strong>Step 4:<\/strong> Boolean Expression - Derive from truth table (SOP or POS)<\/li>\r\n <li><strong>Step 5:<\/strong> Simplification - Use Boolean algebra or K-map<\/li>\r\n <li><strong>Step 6:<\/strong> Logic Diagram - Draw circuit using gates<\/li>\r\n <li><strong>Step 7:<\/strong> Verification - Test with all input combinations<\/li>\r\n <\/ul>\r\n\r\n <h3>Parity Generator & Checker<\/h3>\r\n\r\n <p><strong>Even Parity Generator (3-bit):<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Adds parity bit to make total 1s even<\/span>\r\n\r\nA B C | P (Parity bit)\r\n0 0 0 | 0 (0 ones \u2192 even, add 0)\r\n0 0 1 | 1 (1 one \u2192 odd, add 1)\r\n0 1 0 | 1\r\n0 1 1 | 0\r\n1 0 0 | 1\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1\r\n\r\nP = A \u2295 B \u2295 C\r\n<\/pre><\/div>\r\n\r\n <p><strong>Even Parity Checker:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Checks if total 1s (including parity bit) is even<\/span>\r\n\r\nError = A \u2295 B \u2295 C \u2295 P\r\nError = 0 \u2192 No error (even parity maintained)\r\nError = 1 \u2192 Error detected (odd parity)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Error detection in data transmission, memory systems, communication protocols<\/p>\r\n\r\n <h3>Code Converter Circuits<\/h3>\r\n\r\n <p><strong>1. Binary to Gray Code Converter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">For 3-bit (B\u2082B\u2081B\u2080 \u2192 G\u2082G\u2081G\u2080):<\/span>\r\n\r\nG\u2082 = B\u2082\r\nG\u2081 = B\u2082 \u2295 B\u2081\r\nG\u2080 = B\u2081 \u2295 B\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Gray to Binary Code Converter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">For 3-bit (G\u2082G\u2081G\u2080 \u2192 B\u2082B\u2081B\u2080):<\/span>\r\n\r\nB\u2082 = G\u2082\r\nB\u2081 = B\u2082 \u2295 G\u2081\r\nB\u2080 = B\u2081 \u2295 G\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. BCD to Excess-3 Converter:<\/strong><\/p>\r\n <p>Excess-3 = BCD + 3. Used in arithmetic operations to avoid 0000 representation.<\/p>\r\n\r\n <h3>Arithmetic Logic Unit (ALU)<\/h3>\r\n <p>A combinational circuit that performs arithmetic (add, subtract) and logic (AND, OR, XOR) operations.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Simple 4-function ALU:<\/span>\r\n\r\nInputs: A, B (n-bit data)\r\n S\u2081S\u2080 (2-bit operation select)\r\n\r\nS\u2081 S\u2080 | Operation\r\n0 0 | A AND B\r\n0 1 | A OR B\r\n1 0 | A XOR B\r\n1 1 | A + B\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Design a half adder and verify with truth table 2) Draw a 4:1 MUX circuit 3) Create truth table for 3:8 decoder 4) Design a 2-bit magnitude comparator 5) Implement full adder using two half adders and an OR gate<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-5\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 5<\/span>\r\n <h2>Sequential Circuits<\/h2>\r\n <p>Flip-flops (SR, JK, D, T), Latches, State diagrams, and Timing diagrams<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What are Sequential Circuits?<\/h3>\r\n <p><strong>Sequential circuits<\/strong> are logic circuits whose outputs depend on BOTH present inputs AND past outputs (memory). They have feedback loops and memory elements.<\/p>\r\n\r\n <p><strong>Combinational vs Sequential:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>Combinational<\/th><th>Sequential<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Memory<\/td><td>No memory<\/td><td>Has memory<\/td><\/tr>\r\n <tr><td>Output depends on<\/td><td>Present inputs only<\/td><td>Present inputs + past state<\/td><\/tr>\r\n <tr><td>Feedback<\/td><td>No feedback<\/td><td>Feedback present<\/td><\/tr>\r\n <tr><td>Clock<\/td><td>Not needed<\/td><td>Usually clock-driven<\/td><\/tr>\r\n <tr><td>Elements<\/td><td>Gates only<\/td><td>Gates + Flip-flops<\/td><\/tr>\r\n <tr><td>Examples<\/td><td>Adder, MUX, Decoder<\/td><td>Counter, Register, FSM<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Types of Sequential Circuits<\/h3>\r\n <ul>\r\n <li><strong>Synchronous:<\/strong> State changes only at clock edges (clock-driven)<\/li>\r\n <li><strong>Asynchronous:<\/strong> State changes immediately when inputs change (no clock)<\/li>\r\n <\/ul>\r\n\r\n <h3>Memory Elements<\/h3>\r\n\r\n <p><strong>1. Latch<\/strong><\/p>\r\n <p>Level-sensitive memory element. Changes output when enable signal is HIGH.<\/p>\r\n\r\n <p><strong>2. Flip-Flop<\/strong><\/p>\r\n <p>Edge-sensitive memory element. Changes output only at clock edge (rising or falling).<\/p>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Key Difference:<\/strong> Latch is level-triggered (responds to signal level), Flip-flop is edge-triggered (responds to clock edge transition).<\/div>\r\n\r\n <h3>SR Latch (Set-Reset Latch)<\/h3>\r\n <p>Most basic memory element using NAND or NOR gates.<\/p>\r\n\r\n <p><strong>SR Latch using NOR gates:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nS \u2500\u2500NOR\u2500\u2500\u252c\u2500\u2500\u2500\u2500 Q\r\n \u250c\u2500\u2500\u2500\u2500\u2518\r\n \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2510\r\nR \u2500\u2500NOR\u2500\u2500\u2534\u2500\u2500\u2500\u2500 Q'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS R | Q Q' | State\r\n0 0 | Q Q' | Hold (No change)\r\n0 1 | 0 1 | Reset\r\n1 0 | 1 0 | Set\r\n1 1 | 0 0 | Invalid (Not allowed!)\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(next) = S + R'\u00b7Q\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\u26a0\ufe0f <strong>Invalid State:<\/strong> S=R=1 produces Q=Q'=0, violating the rule that Q and Q' should be complements. Avoid this state!<\/div>\r\n\r\n <p><strong>SR Latch using NAND gates:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table (Active LOW inputs):<\/span>\r\nS\u0304 R\u0304 | Q Q' | State\r\n0 0 | 1 1 | Invalid\r\n0 1 | 1 0 | Set\r\n1 0 | 0 1 | Reset\r\n1 1 | Q Q' | Hold\r\n<\/pre><\/div>\r\n\r\n <h3>Gated SR Latch<\/h3>\r\n <p>SR Latch with enable signal. Changes only when Enable=1.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nS \u2500\u2500\u2510\r\n Enable\u2500\u2500\u2500\u2500 SR Latch \u2500\u2500\u2500\u2500 Q\r\nR \u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500 Q'\r\nEN\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEN S R | Q(next)\r\n0 X X | Q (Hold)\r\n1 0 0 | Q (Hold)\r\n1 0 1 | 0 (Reset)\r\n1 1 0 | 1 (Set)\r\n1 1 1 | Invalid\r\n<\/pre><\/div>\r\n\r\n <h3>D Latch (Data Latch)<\/h3>\r\n <p>Eliminates invalid state of SR latch. Has only one data input.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nD \u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 S\r\n \u2502 SR Latch \u2500\u2500\u2500\u2500 Q\r\n \u2514\u2500\u2500NOT\u2500\u2500 R\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEN D | Q(next)\r\n0 X | Q (Hold)\r\n1 0 | 0\r\n1 1 | 1\r\n\r\n<span class=\"cm\">When EN=1: Q follows D<\/span>\r\n<span class=\"cm\">When EN=0: Q holds previous value<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Flip-Flops (Edge-Triggered)<\/h3>\r\n\r\n <p><strong>Clock Triggering Types:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Positive Edge Triggered:<\/strong> Changes at rising edge (0\u21921) \u2191<\/li>\r\n <li><strong>Negative Edge Triggered:<\/strong> Changes at falling edge (1\u21920) \u2193<\/li>\r\n <\/ul>\r\n\r\n <h3>1. SR Flip-Flop<\/h3>\r\n <p>Edge-triggered version of SR latch.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nS \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 SR\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\nR \u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table (Positive Edge Triggered):<\/span>\r\nS R | Q(t+1) | Comment\r\n0 0 | Q(t) | No change\r\n0 1 | 0 | Reset\r\n1 0 | 1 | Set\r\n1 1 | Invalid | Not allowed\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = S + R'\u00b7Q(t)\r\n<\/pre><\/div>\r\n\r\n <h3>2. JK Flip-Flop<\/h3>\r\n <p>Most versatile flip-flop. Eliminates invalid state by toggling output when J=K=1.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nJ \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 JK\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\nK \u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nJ K | Q(t+1) | Comment\r\n0 0 | Q(t) | No change (Hold)\r\n0 1 | 0 | Reset\r\n1 0 | 1 | Set\r\n1 1 | Q'(t) | Toggle\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = J\u00b7Q'(t) + K'\u00b7Q(t)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Timing Diagram:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510\r\n \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518\r\nJ \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\r\nK \u2500\u2500\u2510 \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\nQ \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">J=0,K=1 \u2192 Reset (Q=0)<\/span>\r\n<span class=\"cm\">J=1,K=0 \u2192 Set (Q=1)<\/span>\r\n<span class=\"cm\">J=1,K=1 \u2192 Toggle<\/span>\r\n<span class=\"cm\">J=0,K=0 \u2192 Hold<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>3. D Flip-Flop (Data\/Delay Flip-Flop)<\/h3>\r\n <p>Stores one bit of data. Output Q follows input D at clock edge.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nD \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 D\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2514\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nD | Q(t+1)\r\n0 | 0\r\n1 | 1\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = D\r\n\r\n<span class=\"cm\">Note: No invalid state, simplest to use<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Shift registers, data storage, delay elements, frequency division<\/p>\r\n\r\n <h3>4. T Flip-Flop (Toggle Flip-Flop)<\/h3>\r\n <p>Toggles output when T=1. Used in counters.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nT \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 T\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2514\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nT | Q(t+1) | Comment\r\n0 | Q(t) | No change\r\n1 | Q'(t) | Toggle\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = T\u00b7Q'(t) + T'\u00b7Q(t) = T \u2295 Q(t)\r\n<\/pre><\/div>\r\n\r\n <p><strong>T Flip-Flop from JK:<\/strong> Connect J and K together \u2192 T input<\/p>\r\n <p><strong>T Flip-Flop from D:<\/strong> Feed Q' XOR T to D input<\/p>\r\n\r\n <h3>Flip-Flop Conversion<\/h3>\r\n\r\n <p><strong>Conversion Table:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Convert From<\/th><th>To<\/th><th>Method<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>JK to D<\/td><td>D<\/td><td>D = J = K'<\/td><\/tr>\r\n <tr><td>JK to T<\/td><td>T<\/td><td>J = K = T<\/td><\/tr>\r\n <tr><td>D to JK<\/td><td>JK<\/td><td>J = D, K = D'<\/td><\/tr>\r\n <tr><td>D to T<\/td><td>T<\/td><td>D = T \u2295 Q<\/td><\/tr>\r\n <tr><td>T to JK<\/td><td>JK<\/td><td>J = K = T<\/td><\/tr>\r\n <tr><td>T to D<\/td><td>D<\/td><td>D = T \u2295 Q<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Example: Convert SR to JK<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Excitation Table Comparison:<\/span>\r\n\r\nQ(t) Q(t+1) | S R | J K\r\n 0 0 | 0 X | 0 X\r\n 0 1 | 1 0 | 1 X\r\n 1 0 | 0 1 | X 1\r\n 1 1 | X 0 | X 0\r\n\r\n<span class=\"cm\">Conversion Logic:<\/span>\r\nS = J\u00b7Q'\r\nR = K\u00b7Q\r\n<\/pre><\/div>\r\n\r\n <h3>Master-Slave Flip-Flop<\/h3>\r\n <p>Two flip-flops in series. Master captures input, slave outputs after clock.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nJ \u2500\u2500\u2510 \u250c\u2500\u2500\u2510 \u250c\u2500\u2500 Q\r\n Master FF \u2502 \u2502 Slave FF \u2502\r\nK \u2500\u2500\u2518 Q\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500 Q \u2500\u2500\u2500\u2518\u2500\u2500 Q'\r\nCLK \u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500NOT\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Operation:<\/span>\r\n1. When CLK=1: Master enabled, Slave disabled\r\n Master captures J, K inputs\r\n2. When CLK=0: Master disabled, Slave enabled\r\n Slave copies Master output\r\n\r\n<span class=\"cm\">Advantage: Prevents race conditions<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Preset and Clear Inputs<\/h3>\r\n <p>Asynchronous inputs that override clock. Used for initialization.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Flip-Flop with Preset (PRE) and Clear (CLR):<\/span>\r\n\r\nPRE \u2500\u2500\u2500\u2500\u2510\r\n \u2502 FF\r\nD \u2500\u2500\u2500\u2500\u2524 \u2500\u2500\u2500\u2500 Q\r\nCLK \u2500\u2500\u2500\u2500\u2524 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2502\r\nCLR \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nPRE CLR | Q Q' | Comment\r\n 0 0 | 1 1 | Invalid\r\n 0 1 | 1 0 | Preset (Set Q=1)\r\n 1 0 | 0 1 | Clear (Set Q=0)\r\n 1 1 | Operates normally with CLK\/D\r\n<\/pre><\/div>\r\n\r\n <h3>State Diagrams<\/h3>\r\n <p>Graphical representation of sequential circuit behavior showing states and transitions.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: 2-bit Binary Counter<\/span>\r\n\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u250c\u2500\u2500\u2502 00 \u2502\u2500\u2500\u2510\r\n \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2518 \u2502\r\n \u2502 \u2193 \u2502\r\n \u2502 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u2502\r\n \u2514\u2500\u2500\u2502 01 \u2502\u2190\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2193\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u250c\u2500\u2500\u2502 10 \u2502\u2190\u2500\u2510\r\n \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2518 \u2502\r\n \u2502 \u2193 \u2502\r\n \u2502 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u2502\r\n \u2514\u2500\u2500\u2502 11 \u2502\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2193\r\n (back to 00)\r\n\r\n<span class=\"cm\">States: 00 \u2192 01 \u2192 10 \u2192 11 \u2192 00...<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>State Table<\/h3>\r\n <p>Tabular representation of state transitions.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: JK Flip-Flop State Table<\/span>\r\n\r\nPresent Inputs | Next\r\nState J K | State\r\n 0 0 0 | 0\r\n 0 0 1 | 0\r\n 0 1 0 | 1\r\n 0 1 1 | 1\r\n 1 0 0 | 1\r\n 1 0 1 | 0\r\n 1 1 0 | 1\r\n 1 1 1 | 0\r\n<\/pre><\/div>\r\n\r\n <h3>Excitation Tables<\/h3>\r\n <p>Shows required inputs to achieve desired state transitions. Used in flip-flop conversions.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Flip-Flop<\/th><th>Q(t)\u2192Q(t+1): 0\u21920<\/th><th>0\u21921<\/th><th>1\u21920<\/th><th>1\u21921<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>SR<\/td><td>S=0, R=X<\/td><td>S=1, R=0<\/td><td>S=0, R=1<\/td><td>S=X, R=0<\/td><\/tr>\r\n <tr><td>JK<\/td><td>J=0, K=X<\/td><td>J=1, K=X<\/td><td>J=X, K=1<\/td><td>J=X, K=0<\/td><\/tr>\r\n <tr><td>D<\/td><td>D=0<\/td><td>D=1<\/td><td>D=0<\/td><td>D=1<\/td><\/tr>\r\n <tr><td>T<\/td><td>T=0<\/td><td>T=1<\/td><td>T=1<\/td><td>T=0<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>X = Don't Care:<\/strong> Can be 0 or 1, doesn't matter. Used for optimization.<\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Draw timing diagram for JK flip-flop with J=1, K=0 2) Design a T flip-flop using D flip-flop 3) Create state diagram for 3-bit up counter 4) Convert D flip-flop to JK flip-flop 5) What is the output of SR latch when S=1, R=1?<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-6\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 6<\/span>\r\n <h2>Counters & Registers<\/h2>\r\n <p>Up\/Down counters, Ring counters, Shift registers, and Applications<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Counter?<\/h3>\r\n <p>A <strong>counter<\/strong> is a sequential circuit that goes through a predetermined sequence of states upon application of clock pulses. Counts number of clock pulses.<\/p>\r\n\r\n <h3>Types of Counters<\/h3>\r\n\r\n <div class=\"feature-grid\">\r\n <div class=\"feature-item\">\u2b06\ufe0f Up Counter: Counts 0\u21921\u21922\u21923...<\/div>\r\n <div class=\"feature-item\">\u2b07\ufe0f Down Counter: Counts 3\u21922\u21921\u21920...<\/div>\r\n <div class=\"feature-item\">\ud83d\udd04 Up\/Down Counter: Both directions<\/div>\r\n <div class=\"feature-item\">\ud83d\udd22 Modulo-N: Counts 0 to N-1<\/div>\r\n <\/div>\r\n\r\n <h3>1. Asynchronous (Ripple) Counter<\/h3>\r\n <p>Flip-flops are NOT clocked simultaneously. Output of one triggers the next.<\/p>\r\n\r\n <p><strong>2-bit Asynchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nCLK \u2500\u2500\u2510 T-FF \u2510 \u250c T-FF \u2510\r\n \u2502 T=1 \u2502Q\u2080 \u2502 T=1 \u2502Q\u2081\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Timing Diagram:<\/span>\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\r\n \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518\r\nQ\u2080 \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\nQ\u2081 \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCount: 00 \u2192 01 \u2192 10 \u2192 11 \u2192 00...\r\n\r\n<span class=\"cm\">MOD-4 Counter (counts 0-3)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-bit Asynchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Counts: 000 \u2192 001 \u2192 010 \u2192 011 \u2192 100 \u2192 101 \u2192 110 \u2192 111 \u2192 000<\/span>\r\n<span class=\"cm\">MOD-8 Counter (8 states)<\/span>\r\n\r\n<span class=\"cm\">Disadvantage: Propagation delay (ripple effect)<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>2. Synchronous Counter<\/h3>\r\n <p>All flip-flops are clocked simultaneously. No ripple delay.<\/p>\r\n\r\n <p><strong>2-bit Synchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit using JK Flip-Flops:<\/span>\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\nJ\u2080=1\u2500\u2500\u2502 JK \u2502\u2500\u2500Q\u2080\u2500\u2500\u2502 JK \u2502\u2500\u2500Q\u2081\r\nK\u2080=1\u2500\u2500\u2502 FF0 \u2502 \u2502 FF1 \u2502\r\nCLK\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518 J\u2081\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n K\u2081\r\n\r\nJ\u2081 = K\u2081 = Q\u2080\r\n\r\n<span class=\"cm\">State Table:<\/span>\r\nQ\u2081 Q\u2080 | J\u2081K\u2081 J\u2080K\u2080 | Next\r\n 0 0 | 0X 11 | 01\r\n 0 1 | 1X 11 | 10\r\n 1 0 | X0 11 | 11\r\n 1 1 | X1 11 | 00\r\n<\/pre><\/div>\r\n\r\n <h3>3. Decade Counter (MOD-10)<\/h3>\r\n <p>Counts from 0 to 9, then resets to 0. Uses 4 flip-flops but only 10 states.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">BCD Counter:<\/span>\r\nCount: 0000 \u2192 0001 \u2192 0010 \u2192 ... \u2192 1001 \u2192 0000\r\n\r\n<span class=\"cm\">IC 7490: Decade Counter chip<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>4. Ring Counter<\/h3>\r\n <p>Shift register with output fed back to input. Circulates single '1' bit.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit Ring Counter:<\/span>\r\n\r\nD-FF\u2080 \u2192 D-FF\u2081 \u2192 D-FF\u2082 \u2192 D-FF\u2083 \u2192\u2510\r\n \u2191 \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Sequence:<\/span>\r\nQ\u2083Q\u2082Q\u2081Q\u2080\r\n1000 \u2192 0100 \u2192 0010 \u2192 0001 \u2192 1000...\r\n\r\n<span class=\"cm\">Applications: State machines, sequence generators<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>5. Johnson Counter (Twisted Ring)<\/h3>\r\n <p>Ring counter with inverted feedback. Has 2N states for N flip-flops.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit Johnson Counter:<\/span>\r\n\r\nD-FF\u2080 \u2192 D-FF\u2081 \u2192 D-FF\u2082 \u2192 D-FF\u2083 \u2192\u2510\r\n \u2191 NOT\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Sequence (8 states):<\/span>\r\n0000 \u2192 1000 \u2192 1100 \u2192 1110 \u2192 1111 \u2192 0111 \u2192 0011 \u2192 0001 \u2192 0000\r\n<\/pre><\/div>\r\n\r\n <h3>Registers<\/h3>\r\n <p>A <strong>register<\/strong> is a group of flip-flops used to store multiple bits of data. Each flip-flop stores one bit.<\/p>\r\n\r\n <h3>1. Parallel-In Parallel-Out (PIPO) Register<\/h3>\r\n <p>All bits loaded and read simultaneously.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit PIPO Register:<\/span>\r\n\r\nD\u2083\u2500\u2500D-FF\u2083\u2500\u2500Q\u2083 D\u2082\u2500\u2500D-FF\u2082\u2500\u2500Q\u2082 D\u2081\u2500\u2500D-FF\u2081\u2500\u2500Q\u2081 D\u2080\u2500\u2500D-FF\u2080\u2500\u2500Q\u2080\r\n \u2502 \u2502 \u2502 \u2502\r\n CLK \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n\r\n<span class=\"cm\">All data loaded at once on clock edge<\/span>\r\n<span class=\"cm\">All data read at once<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>2. Serial-In Serial-Out (SISO) Register<\/h3>\r\n <p>Data shifted in and out one bit at a time. Basic shift register.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit SISO (Right Shift):<\/span>\r\n\r\nDIN \u2500\u2500 D-FF\u2080 \u2500 D-FF\u2081 \u2500 D-FF\u2082 \u2500 D-FF\u2083 \u2500\u2500 DOUT\r\n \u2502 \u2502 \u2502 \u2502\r\n CLK \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n\r\n<span class=\"cm\">Example: Input 1011 (MSB first)<\/span>\r\nCLK State\r\n 0 0000 (Initial)\r\n 1 1000 (Input 1)\r\n 2 1100 (Input 0)\r\n 3 1110 (Input 1)\r\n 4 1111 (Input 1)\r\n<\/pre><\/div>\r\n\r\n <h3>3. Serial-In Parallel-Out (SIPO) Register<\/h3>\r\n <p>Data shifted in serially, read out in parallel. Serial-to-parallel conversion.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Application: UART receiver, SPI communication<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>4. Parallel-In Serial-Out (PISO) Register<\/h3>\r\n <p>Data loaded in parallel, shifted out serially. Parallel-to-serial conversion.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Application: UART transmitter, data serialization<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Shift Register Modes<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Mode<\/th><th>Description<\/th><th>Application<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Right Shift<\/td><td>Bits shift right, divide by 2<\/td><td>Division, serial output<\/td><\/tr>\r\n <tr><td>Left Shift<\/td><td>Bits shift left, multiply by 2<\/td><td>Multiplication, serial output<\/td><\/tr>\r\n <tr><td>Rotate Right<\/td><td>MSB\u2192LSB (circular)<\/td><td>Rotation, code generation<\/td><\/tr>\r\n <tr><td>Rotate Left<\/td><td>LSB\u2192MSB (circular)<\/td><td>Rotation, code generation<\/td><\/tr>\r\n <tr><td>Bidirectional<\/td><td>Shift both directions<\/td><td>Universal shift register<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Universal Shift Register<\/h3>\r\n <p>Can perform all shift operations: left, right, parallel load, parallel read.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Mode Select (S\u2081S\u2080):<\/span>\r\nS\u2081 S\u2080 | Operation\r\n0 0 | No change (Hold)\r\n0 1 | Shift Right\r\n1 0 | Shift Left\r\n1 1 | Parallel Load\r\n\r\n<span class=\"cm\">IC 74195: 4-bit universal shift register<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Applications of Counters<\/h3>\r\n\r\n <ul>\r\n <li><strong>Frequency Division:<\/strong> MOD-N counter divides frequency by N<\/li>\r\n <li><strong>Digital Clock:<\/strong> MOD-60 for seconds\/minutes, MOD-24 for hours<\/li>\r\n <li><strong>Event Counting:<\/strong> Counting products, pulses, events<\/li>\r\n <li><strong>Timing Circuits:<\/strong> Generating time delays<\/li>\r\n <li><strong>Address Generation:<\/strong> Memory addressing in CPUs<\/li>\r\n <li><strong>Sequence Generation:<\/strong> State machines, control logic<\/li>\r\n <\/ul>\r\n\r\n <h3>Applications of Registers<\/h3>\r\n\r\n <ul>\r\n <li><strong>Data Storage:<\/strong> CPU registers (accumulator, program counter)<\/li>\r\n <li><strong>Data Transfer:<\/strong> Buffer between components<\/li>\r\n <li><strong>Serial Communication:<\/strong> UART, SPI, I2C<\/li>\r\n <li><strong>Arithmetic Operations:<\/strong> Shifting for multiply\/divide<\/li>\r\n <li><strong>Timing & Synchronization:<\/strong> Pipeline registers<\/li>\r\n <li><strong>Data Serialization:<\/strong> Parallel to serial conversion<\/li>\r\n <\/ul>\r\n\r\n <h3>Counter ICs<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Type<\/th><th>Description<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>7490<\/td><td>Decade<\/td><td>MOD-10 asynchronous counter<\/td><\/tr>\r\n <tr><td>7493<\/td><td>Binary<\/td><td>4-bit binary counter (MOD-16)<\/td><\/tr>\r\n <tr><td>74190<\/td><td>Up\/Down<\/td><td>Synchronous BCD up\/down counter<\/td><\/tr>\r\n <tr><td>74191<\/td><td>Up\/Down<\/td><td>Synchronous binary up\/down counter<\/td><\/tr>\r\n <tr><td>74193<\/td><td>Up\/Down<\/td><td>4-bit binary up\/down counter<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Design a MOD-6 counter using JK flip-flops 2) Draw timing diagram for 3-bit ripple counter 3) Design a 4-bit SISO shift register 4) What is the output sequence of a 3-bit Johnson counter? 5) Calculate frequency at output of MOD-8 counter if input is 1 MHz<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-7\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 7<\/span>\r\n <h2>Memory Systems<\/h2>\r\n <p>RAM, ROM, SRAM, DRAM, Memory organization, and Address decoding<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is Memory?<\/h3>\r\n <p><strong>Memory<\/strong> is a digital circuit that stores data in binary form. Essential component of all computer systems.<\/p>\r\n\r\n <h3>Memory Classification<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Memory Hierarchy:<\/span>\r\n\r\n Memory\r\n \u2502\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502\r\n Volatile Non-Volatile\r\n (RAM) (ROM)\r\n \u2502 \u2502\r\n \u250c\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502 \u2502 \u2502\r\n SRAM DRAM ROM EPROM\r\n EEPROM\r\n Flash\r\n<\/pre><\/div>\r\n\r\n <h3>1. RAM (Random Access Memory)<\/h3>\r\n <p><strong>Volatile memory:<\/strong> Data lost when power off. Read and Write operations.<\/p>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n\r\n <p><strong>A) SRAM (Static RAM)<\/strong><\/p>\r\n <ul>\r\n <li>Uses flip-flops (6 transistors per bit)<\/li>\r\n <li>Faster than DRAM<\/li>\r\n <li>No refresh required<\/li>\r\n <li>More expensive<\/li>\r\n <li>Lower density<\/li>\r\n <li>Used in: Cache memory, CPU registers<\/li>\r\n <\/ul>\r\n\r\n <p><strong>B) DRAM (Dynamic RAM)<\/strong><\/p>\r\n <ul>\r\n <li>Uses capacitors (1 transistor + 1 capacitor per bit)<\/li>\r\n <li>Slower than SRAM<\/li>\r\n <li>Requires periodic refresh (capacitor leaks)<\/li>\r\n <li>Cheaper<\/li>\r\n <li>Higher density<\/li>\r\n <li>Used in: Main memory (system RAM)<\/li>\r\n <\/ul>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>SRAM<\/th><th>DRAM<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Speed<\/td><td>Fast (2-10 ns)<\/td><td>Slower (50-70 ns)<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Expensive<\/td><td>Cheap<\/td><\/tr>\r\n <tr><td>Density<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Refresh<\/td><td>Not needed<\/td><td>Needed<\/td><\/tr>\r\n <tr><td>Complexity<\/td><td>Complex (6T)<\/td><td>Simple (1T1C)<\/td><\/tr>\r\n <tr><td>Usage<\/td><td>Cache<\/td><td>Main memory<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>2. ROM (Read-Only Memory)<\/h3>\r\n <p><strong>Non-volatile memory:<\/strong> Data retained when power off. Primarily read operations.<\/p>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n\r\n <p><strong>A) Mask ROM<\/strong><\/p>\r\n <ul>\r\n <li>Programmed during manufacturing<\/li>\r\n <li>Cannot be modified<\/li>\r\n <li>Used in: BIOS, firmware, embedded systems<\/li>\r\n <\/ul>\r\n\r\n <p><strong>B) PROM (Programmable ROM)<\/strong><\/p>\r\n <ul>\r\n <li>One-time programmable by user<\/li>\r\n <li>Uses fuses that can be blown<\/li>\r\n <li>Cannot be erased once programmed<\/li>\r\n <\/ul>\r\n\r\n <p><strong>C) EPROM (Erasable PROM)<\/strong><\/p>\r\n <ul>\r\n <li>Can be erased using UV light<\/li>\r\n <li>Reprogrammable<\/li>\r\n <li>Has transparent window on top<\/li>\r\n <li>Erase time: 15-20 minutes<\/li>\r\n <\/ul>\r\n\r\n <p><strong>D) EEPROM (Electrically Erasable PROM)<\/strong><\/p>\r\n <ul>\r\n <li>Can be erased electrically (byte-by-byte)<\/li>\r\n <li>No UV light needed<\/li>\r\n <li>Slower write, faster read<\/li>\r\n <li>Used in: Configuration data, calibration<\/li>\r\n <\/ul>\r\n\r\n <p><strong>E) Flash Memory<\/strong><\/p>\r\n <ul>\r\n <li>Type of EEPROM, erases in blocks<\/li>\r\n <li>Fast, high density<\/li>\r\n <li>Used in: USB drives, SSDs, memory cards<\/li>\r\n <\/ul>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Type<\/th><th>Erase Method<\/th><th>Write Speed<\/th><th>Application<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Mask ROM<\/td><td>Cannot erase<\/td><td>N\/A<\/td><td>BIOS, firmware<\/td><\/tr>\r\n <tr><td>PROM<\/td><td>Cannot erase<\/td><td>Fast<\/td><td>One-time programming<\/td><\/tr>\r\n <tr><td>EPROM<\/td><td>UV light<\/td><td>Slow<\/td><td>Development, testing<\/td><\/tr>\r\n <tr><td>EEPROM<\/td><td>Electrical (byte)<\/td><td>Very slow<\/td><td>Config, calibration<\/td><\/tr>\r\n <tr><td>Flash<\/td><td>Electrical (block)<\/td><td>Medium<\/td><td>Storage, USB, SSD<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Memory Organization<\/h3>\r\n\r\n <p><strong>Memory Specifications:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Capacity:<\/strong> Total number of bits (M \u00d7 N)<\/li>\r\n <li><strong>M:<\/strong> Number of words (addressable locations)<\/li>\r\n <li><strong>N:<\/strong> Number of bits per word (word size)<\/li>\r\n <li><strong>Address lines:<\/strong> log\u2082(M) lines needed<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: 1K \u00d7 8 Memory<\/span>\r\n\r\n1K = 1024 words\r\n8 = 8 bits per word\r\n\r\nTotal capacity: 1024 \u00d7 8 = 8192 bits = 8 Kb = 1 KB\r\n\r\nAddress lines needed: log\u2082(1024) = 10 lines\r\nData lines: 8 lines\r\n\r\n<span class=\"cm\">Memory Block Diagram:<\/span>\r\n\r\nA\u2080-A\u2089 (10 lines) \u2500\u2500\u2500\u2500\u2510\r\n \u2502 1K\u00d78\r\nCS (Chip Select) \u2500\u2500\u2500\u2500\u2500\u2524 Memory \u2500\u2500\u2500\u2500 D\u2080-D\u2087 (8 lines)\r\nR\/W\u0304 (Read\/Write) \u2500\u2500\u2500\u2500\u2500\u2524\r\n \u2514\r\n\r\n<span class=\"cm\">Address Range: 0x000 to 0x3FF (0 to 1023)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Common Memory Sizes:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Specification<\/th><th>Words<\/th><th>Address Bits<\/th><th>Total Capacity<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>256 \u00d7 4<\/td><td>256<\/td><td>8<\/td><td>1 Kb<\/td><\/tr>\r\n <tr><td>1K \u00d7 8<\/td><td>1024<\/td><td>10<\/td><td>8 Kb = 1 KB<\/td><\/tr>\r\n <tr><td>4K \u00d7 8<\/td><td>4096<\/td><td>12<\/td><td>32 Kb = 4 KB<\/td><\/tr>\r\n <tr><td>64K \u00d7 8<\/td><td>65,536<\/td><td>16<\/td><td>512 Kb = 64 KB<\/td><\/tr>\r\n <tr><td>1M \u00d7 8<\/td><td>1,048,576<\/td><td>20<\/td><td>8 Mb = 1 MB<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Memory Expansion<\/h3>\r\n\r\n <p><strong>1. Word Expansion (Increasing Word Size)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Create 1K\u00d716 using two 1K\u00d78 chips<\/span>\r\n\r\nA\u2080-A\u2089 \u2500\u2500\u252c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2500\u2500 D\u2080-D\u2087\r\n \u2502 Chip 1\r\nCS \u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2500\u2500 D\u2088-D\u2081\u2085\r\n \u2502 Chip 2\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Same addresses, more data bits<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Word Count Expansion (Increasing Number of Words)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Create 2K\u00d78 using two 1K\u00d78 chips<\/span>\r\n\r\nA\u2080-A\u2089 \u2500\u2500\u252c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2510\r\n \u2502 Chip 1 \u251c\u2500\u2500\u2500 D\u2080-D\u2087\r\nA\u2081\u2080 \u2500\u2500\u2500\u2500\u2524 \u2502\r\nDecoder \u2502 1K\u00d78 \u2500\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500 Chip 2\r\n\r\n<span class=\"cm\">A\u2081\u2080=0: Chip 1 (0x000-0x3FF)<\/span>\r\n<span class=\"cm\">A\u2081\u2080=1: Chip 2 (0x400-0x7FF)<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Address Decoding<\/h3>\r\n <p>Process of selecting specific memory chip based on address.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Linear Decoding (Simple but wasteful):<\/span>\r\n\r\nA\u2081\u2080 \u2500\u2500NOT\u2500\u2500 CS\u0304\u2081 (Chip 1: A\u2081\u2080=0)\r\nA\u2081\u2080 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 CS\u0304\u2082 (Chip 2: A\u2081\u2080=1)\r\n\r\n<span class=\"cm\">Full Decoding (Using Decoder):<\/span>\r\n\r\nA\u2081\u2080-A\u2081\u2081 \u2500\u2500\u2500\u2510\r\n 2:4 CS\u0304\u2080 \u2192 Chip 0\r\n Decoder CS\u0304\u2081 \u2192 Chip 1\r\n CS\u0304\u2082 \u2192 Chip 2\r\n CS\u0304\u2083 \u2192 Chip 3\r\n<\/pre><\/div>\r\n\r\n <h3>Memory Timing<\/h3>\r\n\r\n <p><strong>Read Cycle Timing:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Memory Read Timing Diagram:<\/span>\r\n\r\nAddress \u2500\u2500\u2510 Valid Address \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCS\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 (High for Read)\r\n\r\nData \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 Valid Data \u250c\u2500\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190\u2500 tACC \u2500\u2192 (Access Time)\r\n\r\n<span class=\"cm\">tACC: Time from address valid to data valid<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Write Cycle Timing:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nAddress \u2500\u2500\u2510 Valid Address \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCS\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500 (Low for Write)\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nData \u2500\u2500\u2500\u2500\u2500\u2510 Valid Data \u250c\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190\u2500 tWR \u2500\u2192 (Write Time)\r\n<\/pre><\/div>\r\n\r\n <h3>Memory ICs<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Type<\/th><th>Capacity<\/th><th>Organization<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>2114<\/td><td>SRAM<\/td><td>4 Kb<\/td><td>1K \u00d7 4<\/td><\/tr>\r\n <tr><td>6116<\/td><td>SRAM<\/td><td>16 Kb<\/td><td>2K \u00d7 8<\/td><\/tr>\r\n <tr><td>6264<\/td><td>SRAM<\/td><td>64 Kb<\/td><td>8K \u00d7 8<\/td><\/tr>\r\n <tr><td>2732<\/td><td>EPROM<\/td><td>32 Kb<\/td><td>4K \u00d7 8<\/td><\/tr>\r\n <tr><td>2764<\/td><td>EPROM<\/td><td>64 Kb<\/td><td>8K \u00d7 8<\/td><\/tr>\r\n <tr><td>27C256<\/td><td>EPROM<\/td><td>256 Kb<\/td><td>32K \u00d7 8<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Calculate address lines needed for 16K \u00d7 8 memory 2) Design memory system with 4K \u00d7 8 using two 2K \u00d7 8 chips 3) Compare SRAM vs DRAM 4) What is address range for 1K \u00d7 8 memory starting at 0x2000? 5) Draw timing diagram for memory read cycle<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-8\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 8<\/span>\r\n <h2>Advanced Topics<\/h2>\r\n <p>PLDs, FPGAs, Karnaugh Maps, Quine-McCluskey method, and Modern Digital Design<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>Karnaugh Maps (K-Maps)<\/h3>\r\n <p><strong>Karnaugh Map<\/strong> is a graphical method for simplifying Boolean expressions. Alternative to Boolean algebra.<\/p>\r\n\r\n <p><strong>2-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> B\r\nA 0 1\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n0 \u2502 0 1\r\n1 \u2502 2 3\r\n\r\n<span class=\"cm\">Example: F(A,B) = \u03a3m(1,2,3)<\/span>\r\n\r\n B\r\nA 0 1\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n0 \u2502 0 1\r\n1 \u2502 1 1\r\n\r\n<span class=\"cm\">Grouping:<\/span>\r\nGroup 1 (1,3): B\r\nGroup 2 (2,3): A\r\n\r\nF = A + B\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 3 2\r\n 1 \u2502 4 5 7 6\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,7)<\/span>\r\n\r\n BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 1 0\r\n 1 \u2502 0 1 1 0\r\n\r\n<span class=\"cm\">Grouping: Vertical column (1,3,5,7)<\/span>\r\nF = C\r\n\r\n<span class=\"cm\">Gray code ordering! (00,01,11,10)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>4-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> CD\r\nAB 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 00 \u2502 0 1 3 2\r\n 01 \u2502 4 5 7 6\r\n 11 \u2502 12 13 15 14\r\n 10 \u2502 8 9 11 10\r\n\r\n<span class=\"cm\">Rules for Grouping:<\/span>\r\n1. Group size: 1, 2, 4, 8, 16 (powers of 2)\r\n2. Groups should be rectangular\r\n3. Make largest possible groups\r\n4. Groups can overlap\r\n5. Groups can wrap around edges\r\n6. Minimize number of groups\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: Simplify using K-Map<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">F(A,B,C,D) = \u03a3m(0,2,5,7,8,10,13,15)<\/span>\r\n\r\n CD\r\nAB 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 00 \u2502 1 0 0 1 Group 1: m(0,2,8,10) = B'D'\r\n 01 \u2502 0 1 1 0 Group 2: m(5,7,13,15) = BD\r\n 11 \u2502 0 1 1 0\r\n 10 \u2502 1 0 0 1\r\n\r\nF = B'D' + BD = B \u2295 D\r\n<\/pre><\/div>\r\n\r\n <p><strong>Don't Care Conditions (X):<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">F(A,B,C) = \u03a3m(1,3,7) + d(5,6)<\/span>\r\n<span class=\"cm\">d = don't care (can be 0 or 1)<\/span>\r\n\r\nUse X strategically to make larger groups!\r\n\r\n BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 1 0\r\n 1 \u2502 0 X 1 X\r\n\r\n<span class=\"cm\">Include d(5) in group with m(1,7)<\/span>\r\nF = C\r\n<\/pre><\/div>\r\n\r\n <h3>Quine-McCluskey Method<\/h3>\r\n <p>Tabular method for simplification. Better for >4 variables and computer implementation.<\/p>\r\n\r\n <p><strong>Steps:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Step 1:<\/strong> List minterms in binary grouped by number of 1s<\/li>\r\n <li><strong>Step 2:<\/strong> Compare adjacent groups, combine terms differing by 1 bit<\/li>\r\n <li><strong>Step 3:<\/strong> Replace differing bit with dash (-)<\/li>\r\n <li><strong>Step 4:<\/strong> Repeat until no more combinations possible<\/li>\r\n <li><strong>Step 5:<\/strong> Create prime implicant table<\/li>\r\n <li><strong>Step 6:<\/strong> Select minimum set of prime implicants<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,6,7)<\/span>\r\n\r\n<span class=\"cm\">Step 1: List by number of 1s<\/span>\r\nGroup 0: m\u2081 = 001\r\nGroup 1: m\u2083 = 011\r\n m\u2085 = 101\r\nGroup 2: m\u2086 = 110\r\n m\u2087 = 111\r\n\r\n<span class=\"cm\">Step 2: Combine (differ by 1 bit)<\/span>\r\nm\u2081,m\u2083: 0-1 (BC)\r\nm\u2081,m\u2085: -01 (A'C)\r\nm\u2083,m\u2087: -11 (BC)\r\nm\u2085,m\u2087: 1-1 (AC)\r\nm\u2086,m\u2087: 11- (AB)\r\n\r\n<span class=\"cm\">Step 3: Prime Implicants<\/span>\r\nBC, A'C, AC, AB\r\n\r\n<span class=\"cm\">Step 4: Minimum cover<\/span>\r\nF = A'C + AB + BC\r\n<\/pre><\/div>\r\n\r\n <h3>Programmable Logic Devices (PLDs)<\/h3>\r\n <p>ICs that can be programmed to implement custom logic functions. User-configurable hardware.<\/p>\r\n\r\n <h3>Types of PLDs<\/h3>\r\n\r\n <p><strong>1. PROM (Programmable ROM)<\/strong><\/p>\r\n <ul>\r\n <li>Fixed AND array, programmable OR array<\/li>\r\n <li>Simple, but limited flexibility<\/li>\r\n <\/ul>\r\n\r\n <p><strong>2. PAL (Programmable Array Logic)<\/strong><\/p>\r\n <ul>\r\n <li>Programmable AND array, fixed OR array<\/li>\r\n <li>Fast, low cost<\/li>\r\n <li>Cannot share product terms between outputs<\/li>\r\n <\/ul>\r\n\r\n <p><strong>3. PLA (Programmable Logic Array)<\/strong><\/p>\r\n <ul>\r\n <li>Both AND and OR arrays programmable<\/li>\r\n <li>More flexible than PAL<\/li>\r\n <li>Can share product terms<\/li>\r\n <li>Slower than PAL<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">PLD Structure:<\/span>\r\n\r\nInputs \u2192 AND Array \u2192 OR Array \u2192 Outputs\r\n\r\n<span class=\"cm\">PAL: Programmable AND, Fixed OR<\/span>\r\n<span class=\"cm\">PLA: Programmable AND, Programmable OR<\/span>\r\n<span class=\"cm\">PROM: Fixed AND, Programmable OR<\/span>\r\n<\/pre><\/div>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>PAL<\/th><th>PLA<\/th><th>PROM<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>AND Array<\/td><td>Programmable<\/td><td>Programmable<\/td><td>Fixed<\/td><\/tr>\r\n <tr><td>OR Array<\/td><td>Fixed<\/td><td>Programmable<\/td><td>Programmable<\/td><\/tr>\r\n <tr><td>Speed<\/td><td>Fast<\/td><td>Medium<\/td><td>Fast<\/td><\/tr>\r\n <tr><td>Flexibility<\/td><td>Medium<\/td><td>High<\/td><td>Low<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Low<\/td><td>Medium<\/td><td>Low<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Complex PLDs (CPLDs)<\/h3>\r\n <p>Multiple PAL\/PLA blocks connected via programmable interconnects.<\/p>\r\n\r\n <ul>\r\n <li>More logic capacity than simple PLDs<\/li>\r\n <li>Non-volatile (retains configuration when powered off)<\/li>\r\n <li>Predictable timing<\/li>\r\n <li>Examples: Xilinx CoolRunner, Altera MAX<\/li>\r\n <li>Applications: Glue logic, state machines, interface logic<\/li>\r\n <\/ul>\r\n\r\n <h3>Field-Programmable Gate Arrays (FPGAs)<\/h3>\r\n <p>Most advanced and flexible PLDs. Array of configurable logic blocks (CLBs).<\/p>\r\n\r\n <p><strong>FPGA Structure:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502<\/span>\r\n<span class=\"cm\">\u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502 \u2190 Configurable Logic Blocks<\/span>\r\n<span class=\"cm\">\u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502<\/span>\r\n<span class=\"cm\">\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/span>\r\n Programmable Interconnects\r\n\r\n<span class=\"cm\">Each CLB contains:<\/span>\r\n- Look-Up Tables (LUTs) for logic\r\n- Flip-flops for storage\r\n- Multiplexers for routing\r\n<\/pre><\/div>\r\n\r\n <p><strong>FPGA Features:<\/strong><\/p>\r\n <ul>\r\n <li>Very high logic capacity (millions of gates)<\/li>\r\n <li>Reconfigurable (can be reprogrammed)<\/li>\r\n <li>Contains RAM blocks, DSP blocks, I\/O blocks<\/li>\r\n <li>Volatile configuration (needs external memory)<\/li>\r\n <li>Complex, requires specialized tools<\/li>\r\n <\/ul>\r\n\r\n <p><strong>FPGA vs CPLD:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>CPLD<\/th><th>FPGA<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Capacity<\/td><td>10K gates<\/td><td>1M+ gates<\/td><\/tr>\r\n <tr><td>Architecture<\/td><td>PAL-based<\/td><td>LUT-based<\/td><\/tr>\r\n <tr><td>Configuration<\/td><td>Non-volatile<\/td><td>Volatile (SRAM)<\/td><\/tr>\r\n <tr><td>Timing<\/td><td>Predictable<\/td><td>Unpredictable<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Use<\/td><td>Simple logic<\/td><td>Complex systems<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>FPGA Applications<\/h3>\r\n\r\n <ul>\r\n <li><strong>Prototyping:<\/strong> ASIC design verification<\/li>\r\n <li><strong>DSP:<\/strong> Signal processing, image processing<\/li>\r\n <li><strong>Communication:<\/strong> Modems, routers, base stations<\/li>\r\n <li><strong>Aerospace:<\/strong> Satellites, avionics (radiation-tolerant)<\/li>\r\n <li><strong>Industrial:<\/strong> Motor control, robotics<\/li>\r\n <li><strong>AI\/ML:<\/strong> Neural network acceleration<\/li>\r\n <li><strong>Automotive:<\/strong> ADAS, autonomous driving<\/li>\r\n <li><strong>Medical:<\/strong> Medical imaging, diagnostics<\/li>\r\n <\/ul>\r\n\r\n <h3>FPGA Vendors<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Vendor<\/th><th>FPGA Family<\/th><th>Features<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Xilinx (AMD)<\/td><td>Spartan, Artix, Kintex, Virtex<\/td><td>Market leader, high performance<\/td><\/tr>\r\n <tr><td>Intel (Altera)<\/td><td>Cyclone, Arria, Stratix<\/td><td>Good tools, wide adoption<\/td><\/tr>\r\n <tr><td>Lattice<\/td><td>iCE40, ECP5, CrossLink<\/td><td>Low power, small size<\/td><\/tr>\r\n <tr><td>Microchip<\/td><td>PolarFire, IGLOO<\/td><td>Low power, secure<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Hardware Description Languages (HDLs)<\/h3>\r\n <p>Used to design and program FPGAs\/CPLDs.<\/p>\r\n\r\n <p><strong>1. Verilog<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">\/\/ 2-to-1 Multiplexer in Verilog<\/span>\r\n<span class=\"kw\">module<\/span> mux2to1 (\r\n <span class=\"kw\">input<\/span> a, b, sel,\r\n <span class=\"kw\">output<\/span> y\r\n);\r\n <span class=\"kw\">assign<\/span> y = sel ? b : a;\r\n<span class=\"kw\">endmodule<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. VHDL<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">-- 2-to-1 Multiplexer in VHDL<\/span>\r\n<span class=\"kw\">entity<\/span> mux2to1 <span class=\"kw\">is<\/span>\r\n <span class=\"kw\">port<\/span> (a, b, sel : <span class=\"kw\">in<\/span> std_logic;\r\n y : <span class=\"kw\">out<\/span> std_logic);\r\n<span class=\"kw\">end<\/span> mux2to1;\r\n\r\n<span class=\"kw\">architecture<\/span> behav <span class=\"kw\">of<\/span> mux2to1 <span class=\"kw\">is<\/span>\r\n<span class=\"kw\">begin<\/span>\r\n y <= b <span class=\"kw\">when<\/span> sel = '1' <span class=\"kw\">else<\/span> a;\r\n<span class=\"kw\">end<\/span> behav;\r\n<\/pre><\/div>\r\n\r\n <h3>ASIC (Application-Specific Integrated Circuit)<\/h3>\r\n <p>Custom-designed ICs for specific applications. Not programmable like FPGAs.<\/p>\r\n\r\n <p><strong>ASIC vs FPGA:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>ASIC<\/th><th>FPGA<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Flexibility<\/td><td>Fixed (cannot change)<\/td><td>Reconfigurable<\/td><\/tr>\r\n <tr><td>Development Cost<\/td><td>Very high (millions)<\/td><td>Low<\/td><\/tr>\r\n <tr><td>Unit Cost<\/td><td>Low (in volume)<\/td><td>High<\/td><\/tr>\r\n <tr><td>Performance<\/td><td>Highest<\/td><td>Lower<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Lowest<\/td><td>Higher<\/td><\/tr>\r\n <tr><td>Time-to-Market<\/td><td>Long (months)<\/td><td>Short (days)<\/td><\/tr>\r\n <tr><td>Use Case<\/td><td>High volume products<\/td><td>Low volume, prototyping<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Modern Digital Design Flow<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. Specification<\/span>\r\n Define requirements, features, constraints\r\n \u2193\r\n<span class=\"cm\">2. Architecture Design<\/span>\r\n Block diagrams, high-level design\r\n \u2193\r\n<span class=\"cm\">3. RTL Design (HDL Coding)<\/span>\r\n Write Verilog\/VHDL code\r\n \u2193\r\n<span class=\"cm\">4. Simulation & Verification<\/span>\r\n Testbenches, functional verification\r\n \u2193\r\n<span class=\"cm\">5. Synthesis<\/span>\r\n Convert HDL to gate-level netlist\r\n \u2193\r\n<span class=\"cm\">6. Place & Route<\/span>\r\n Map logic to physical layout\r\n \u2193\r\n<span class=\"cm\">7. Timing Analysis<\/span>\r\n Check timing constraints, optimize\r\n \u2193\r\n<span class=\"cm\">8. Bitstream Generation<\/span>\r\n Create configuration file for FPGA\r\n \u2193\r\n<span class=\"cm\">9. Programming & Testing<\/span>\r\n Load onto hardware, test in real environment\r\n<\/pre><\/div>\r\n\r\n <h3>Timing Concepts<\/h3>\r\n\r\n <p><strong>Setup Time (tsu):<\/strong> Minimum time data must be stable BEFORE clock edge<\/p>\r\n <p><strong>Hold Time (th):<\/strong> Minimum time data must be stable AFTER clock edge<\/p>\r\n <p><strong>Clock-to-Q Delay (tCQ):<\/strong> Time from clock edge to output change<\/p>\r\n <p><strong>Propagation Delay (tp):<\/strong> Time for signal to pass through gate<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Timing Diagram:<\/span>\r\n\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\n\r\nDATA \u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190tsu\u2192 \u2190th\u2192\r\n \u2191 CLK edge\r\n\r\n<span class=\"cm\">Violation:<\/span>\r\n- Setup Violation: Data changes too close to clock edge\r\n- Hold Violation: Data changes too soon after clock edge\r\n<\/pre><\/div>\r\n\r\n <h3>Clock Frequency & Period<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Maximum Clock Frequency:<\/span>\r\n\r\nfmax = 1 \/ (tCQ + tlogic + tsu)\r\n\r\nWhere:\r\ntCQ = Clock-to-Q delay of source FF\r\ntlogic = Combinational logic delay\r\ntsu = Setup time of destination FF\r\n\r\n<span class=\"cm\">Example:<\/span>\r\ntCQ = 2 ns, tlogic = 8 ns, tsu = 1 ns\r\nfmax = 1 \/ (2+8+1) ns = 1\/11 ns = 90.9 MHz\r\n<\/pre><\/div>\r\n\r\n <h3>Metastability<\/h3>\r\n <p>When a flip-flop violates setup\/hold time, output may become unstable (neither 0 nor 1).<\/p>\r\n\r\n <ul>\r\n <li><strong>Cause:<\/strong> Asynchronous inputs violating timing<\/li>\r\n <li><strong>Solution:<\/strong> Use synchronizers (2-FF chain)<\/li>\r\n <li><strong>Impact:<\/strong> Unpredictable behavior, system failure<\/li>\r\n <\/ul>\r\n\r\n <h3>Power Consumption in Digital Circuits<\/h3>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Dynamic Power:<\/strong> Power when switching (CV\u00b2f)<\/li>\r\n <li><strong>Static Power:<\/strong> Leakage power when idle<\/li>\r\n <li><strong>Short-Circuit Power:<\/strong> During transition<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Dynamic Power:<\/span>\r\nP = C \u00d7 V\u00b2 \u00d7 f \u00d7 \u03b1\r\n\r\nC = Load capacitance\r\nV = Supply voltage\r\nf = Clock frequency\r\n\u03b1 = Switching activity factor (0 to 1)\r\n\r\n<span class=\"cm\">Reducing Power:<\/span>\r\n- Lower voltage\r\n- Reduce clock frequency\r\n- Clock gating (disable unused blocks)\r\n- Power gating (turn off unused blocks)\r\n<\/pre><\/div>\r\n\r\n <h3>Future of Digital Logic Design<\/h3>\r\n\r\n <ul>\r\n <li><strong>3D ICs:<\/strong> Stacking multiple die layers<\/li>\r\n <li><strong>Quantum Computing:<\/strong> Qubits instead of bits<\/li>\r\n <li><strong>Neuromorphic Computing:<\/strong> Brain-inspired architectures<\/li>\r\n <li><strong>Optical Computing:<\/strong> Light-based logic<\/li>\r\n <li><strong>DNA Computing:<\/strong> Biological computation<\/li>\r\n <li><strong>Spintronics:<\/strong> Using electron spin<\/li>\r\n <\/ul>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Simplify F(A,B,C,D) = \u03a3m(0,1,2,5,8,9,10) using K-map 2) Compare PAL, PLA, and PROM 3) List advantages of FPGAs over ASICs 4) Calculate maximum clock frequency if tCQ=3ns, tlogic=10ns, tsu=2ns 5) Draw a 3-variable K-map and group minterms<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"congrats\">\r\n <h2>\ud83c\udf89 Congratulations!<\/h2>\r\n <p>You've completed Digital Logic Design course! You now have solid foundation in DLD - from number systems to advanced FPGAs and modern digital design. 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\n\t\t\t\t\t\r\n\r\n\r\n \r\n \r\n Digital Logic Design (DLD) Complete Course \u2013 University Level \u2013 Pak Notes Hub<\/title>\r\n <link href=\"https:\/\/fonts.googleapis.com\/css2?family=Inter:wght@400;500;600;700&family=Fira+Code:wght@400;500&display=swap\" rel=\"stylesheet\"\/>\r\n <style>\r\n *, *::before, *::after { box-sizing: border-box; margin: 0; padding: 0; }\r\n :root {\r\n --green:#1a7a4a; --green-dark:#145f38; --green-light:#e8f5ee;\r\n --teal:#17a589; --accent:#f0b127; --dark:#1c2833; --mid:#566573;\r\n --light:#f4f6f7; --code-bg:#f0f4f8; --code-border:#2e86c1;\r\n --note-bg:#fef9e7; --note-border:#f0b127; --white:#ffffff;\r\n --radius:10px; --shadow:0 4px 24px rgba(26,122,74,.10);\r\n }\r\n html { scroll-behavior:smooth; }\r\n body { font-family:'Inter',sans-serif; background:#f2f6f3; color:var(--dark); line-height:1.7; font-size:15px; }\r\n\r\n \/* NAV *\/\r\n nav { position:sticky; top:0; z-index:100; background:var(--green-dark); padding:0 2rem; display:flex; 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class=\"hero-tag\">\u26a1 University \/ College Level \u2014 BS Computer Science \/ Computer Engineering \/ Electrical Engineering<\/div>\r\n <h1>Digital Logic Design<br\/><span>Complete Course<\/span><\/h1>\r\n <p>Number Systems \u00b7 Boolean Algebra \u00b7 Logic Gates \u00b7 Combinational & Sequential Circuits \u2014 Complete Guide in Easy English<\/p>\r\n <div class=\"hero-pills\">\r\n <span class=\"pill\">\ud83d\udcda 8 Units<\/span>\r\n <span class=\"pill\">\ud83c\udf93 University Level<\/span>\r\n <span class=\"pill\">\u26a1 Circuit Diagrams<\/span>\r\n <span class=\"pill\">\ud83d\udcdd Truth Tables<\/span>\r\n <span class=\"pill\">\ud83d\udd25 Practical Examples<\/span>\r\n <\/div>\r\n<\/section>\r\n\r\n<div class=\"page-wrap\">\r\n\r\n <aside class=\"sidebar\">\r\n <div class=\"sidebar-title\">\ud83d\udccb Course Contents<\/div>\r\n <ul class=\"toc-list\" id=\"toc-nav\">\r\n <li><a href=\"#toc-section\"><span class=\"toc-num\">\ud83d\udccb<\/span> Contents<\/a><\/li>\r\n <li><a href=\"#unit-1\"><span class=\"toc-num\">1<\/span> Number Systems<\/a><\/li>\r\n <li><a href=\"#unit-2\"><span class=\"toc-num\">2<\/span> Boolean Algebra<\/a><\/li>\r\n <li><a href=\"#unit-3\"><span class=\"toc-num\">3<\/span> Logic Gates<\/a><\/li>\r\n <li><a href=\"#unit-4\"><span class=\"toc-num\">4<\/span> Combinational Circuits<\/a><\/li>\r\n <li><a href=\"#unit-5\"><span class=\"toc-num\">5<\/span> Sequential Circuits<\/a><\/li>\r\n <li><a href=\"#unit-6\"><span class=\"toc-num\">6<\/span> Counters & Registers<\/a><\/li>\r\n <li><a href=\"#unit-7\"><span class=\"toc-num\">7<\/span> Memory Systems<\/a><\/li>\r\n <li><a href=\"#unit-8\"><span class=\"toc-num\">8<\/span> Advanced Topics<\/a><\/li>\r\n <\/ul>\r\n <\/aside>\r\n\r\n <main>\r\n\r\n <div id=\"toc-section\">\r\n <div class=\"toc-card-header\"><h2>\ud83d\udccb Table of Contents \u2014 8 Units<\/h2><\/div>\r\n <div class=\"toc-card-body\">\r\n <div class=\"toc-grid\">\r\n <a class=\"toc-item\" href=\"#unit-1\"><span class=\"toc-badge\">1<\/span> Number Systems & Codes<\/a>\r\n <a class=\"toc-item\" href=\"#unit-2\"><span class=\"toc-badge\">2<\/span> Boolean Algebra<\/a>\r\n <a class=\"toc-item\" href=\"#unit-3\"><span class=\"toc-badge\">3<\/span> Logic Gates<\/a>\r\n <a class=\"toc-item\" href=\"#unit-4\"><span class=\"toc-badge\">4<\/span> Combinational Circuits<\/a>\r\n <a class=\"toc-item\" href=\"#unit-5\"><span class=\"toc-badge\">5<\/span> Sequential Circuits<\/a>\r\n <a class=\"toc-item\" href=\"#unit-6\"><span class=\"toc-badge\">6<\/span> Counters & Registers<\/a>\r\n <a class=\"toc-item\" href=\"#unit-7\"><span class=\"toc-badge\">7<\/span> Memory Systems<\/a>\r\n <a class=\"toc-item\" href=\"#unit-8\"><span class=\"toc-badge\">8<\/span> Advanced Topics<\/a>\r\n <\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-1\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 1<\/span>\r\n <h2>Number Systems & Codes<\/h2>\r\n <p>Understanding Binary, Octal, Decimal, Hexadecimal, BCD, Gray Code, ASCII and conversions<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Number System?<\/h3>\r\n <p>A <strong>number system<\/strong> is a mathematical notation for representing numbers using a consistent set of digits or symbols. In digital electronics and computers, different number systems are used to represent data.<\/p>\r\n\r\n <h3>Types of Number Systems<\/h3>\r\n \r\n <table class=\"data-table\">\r\n <thead><tr><th>System<\/th><th>Base<\/th><th>Digits Used<\/th><th>Example<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td><strong>Binary<\/strong><\/td><td>2<\/td><td>0, 1<\/td><td>(1010)\u2082<\/td><\/tr>\r\n <tr><td><strong>Octal<\/strong><\/td><td>8<\/td><td>0-7<\/td><td>(752)\u2088<\/td><\/tr>\r\n <tr><td><strong>Decimal<\/strong><\/td><td>10<\/td><td>0-9<\/td><td>(125)\u2081\u2080<\/td><\/tr>\r\n <tr><td><strong>Hexadecimal<\/strong><\/td><td>16<\/td><td>0-9, A-F<\/td><td>(3A7)\u2081\u2086<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>1. Binary Number System (Base 2)<\/h3>\r\n <p><strong>Binary<\/strong> is the fundamental language of computers and digital circuits. It uses only two digits: <strong>0<\/strong> and <strong>1<\/strong>.<\/p>\r\n\r\n <p><strong>Why Binary?<\/strong><\/p>\r\n <ul>\r\n <li>Digital circuits work with two states: ON (1) and OFF (0)<\/li>\r\n <li>Easy to implement using electronic switches (transistors)<\/li>\r\n <li>High noise immunity (clear distinction between 0 and 1)<\/li>\r\n <li>All data in computers is ultimately stored in binary<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Binary Number Representation<\/span>\r\n\r\nPosition: 7 6 5 4 3 2 1 0\r\nValue: 128 64 32 16 8 4 2 1\r\nBinary: 1 0 1 0 1 1 0 1\r\n\r\n(10101101)\u2082 = 128 + 32 + 8 + 4 + 1 = (173)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>2. Decimal Number System (Base 10)<\/h3>\r\n <p>The standard number system we use in everyday life. Uses digits 0-9.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\nPosition: 3 2 1 0\r\nValue: 1000 100 10 1\r\nDecimal: 5 2 7 3\r\n\r\n(5273)\u2081\u2080 = 5\u00d710\u00b3 + 2\u00d710\u00b2 + 7\u00d710\u00b9 + 3\u00d710\u2070 = 5000 + 200 + 70 + 3\r\n<\/pre><\/div>\r\n\r\n <h3>3. Octal Number System (Base 8)<\/h3>\r\n <p>Uses digits 0-7. Often used as a shorthand for binary (each octal digit = 3 binary bits).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\nPosition: 2 1 0\r\nValue: 64 8 1\r\nOctal: 7 5 2\r\n\r\n(752)\u2088 = 7\u00d78\u00b2 + 5\u00d78\u00b9 + 2\u00d78\u2070 = 448 + 40 + 2 = (490)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>4. Hexadecimal Number System (Base 16)<\/h3>\r\n <p>Uses digits 0-9 and letters A-F (A=10, B=11, C=12, D=13, E=14, F=15). Widely used in programming and memory addressing.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>1<\/td><\/tr>\r\n <tr><td>10<\/td><td>1010<\/td><td>A<\/td><\/tr>\r\n <tr><td>11<\/td><td>1011<\/td><td>B<\/td><\/tr>\r\n <tr><td>12<\/td><td>1100<\/td><td>C<\/td><\/tr>\r\n <tr><td>13<\/td><td>1101<\/td><td>D<\/td><\/tr>\r\n <tr><td>14<\/td><td>1110<\/td><td>E<\/td><\/tr>\r\n <tr><td>15<\/td><td>1111<\/td><td>F<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"code-block\"><pre>\r\n(3A7)\u2081\u2086 = 3\u00d716\u00b2 + 10\u00d716\u00b9 + 7\u00d716\u2070 = 768 + 160 + 7 = (935)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <h3>Number System Conversions<\/h3>\r\n\r\n <p><strong>1. Binary to Decimal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (1101)\u2082 to Decimal<\/span>\r\n\r\n(1101)\u2082 = 1\u00d72\u00b3 + 1\u00d72\u00b2 + 0\u00d72\u00b9 + 1\u00d72\u2070\r\n = 8 + 4 + 0 + 1\r\n = (13)\u2081\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Decimal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (25)\u2081\u2080 to Binary<\/span>\r\n\r\n25 \u00f7 2 = 12 remainder 1 (LSB)\r\n12 \u00f7 2 = 6 remainder 0\r\n6 \u00f7 2 = 3 remainder 0\r\n3 \u00f7 2 = 1 remainder 1\r\n1 \u00f7 2 = 0 remainder 1 (MSB)\r\n\r\nRead from bottom to top: (11001)\u2082\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. Binary to Octal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Group binary digits in groups of 3 from right to left<\/span>\r\n\r\n(101110101)\u2082 \r\n= 101 110 101\r\n= 5 6 5\r\n= (565)\u2088\r\n<\/pre><\/div>\r\n\r\n <p><strong>4. Binary to Hexadecimal<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Group binary digits in groups of 4 from right to left<\/span>\r\n\r\n(10111010)\u2082\r\n= 1011 1010\r\n= B A\r\n= (BA)\u2081\u2086\r\n<\/pre><\/div>\r\n\r\n <p><strong>5. Octal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Convert each octal digit to 3-bit binary<\/span>\r\n\r\n(746)\u2088\r\n7 = 111\r\n4 = 100\r\n6 = 110\r\n= (111100110)\u2082\r\n<\/pre><\/div>\r\n\r\n <p><strong>6. Hexadecimal to Binary<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Convert each hex digit to 4-bit binary<\/span>\r\n\r\n(2F)\u2081\u2086\r\n2 = 0010\r\nF = 1111\r\n= (00101111)\u2082\r\n<\/pre><\/div>\r\n\r\n <h3>Quick Conversion Table<\/h3>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Octal<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0<\/td><td>0<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>1<\/td><td>1<\/td><\/tr>\r\n <tr><td>2<\/td><td>0010<\/td><td>2<\/td><td>2<\/td><\/tr>\r\n <tr><td>3<\/td><td>0011<\/td><td>3<\/td><td>3<\/td><\/tr>\r\n <tr><td>4<\/td><td>0100<\/td><td>4<\/td><td>4<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>5<\/td><td>5<\/td><\/tr>\r\n <tr><td>6<\/td><td>0110<\/td><td>6<\/td><td>6<\/td><\/tr>\r\n <tr><td>7<\/td><td>0111<\/td><td>7<\/td><td>7<\/td><\/tr>\r\n <tr><td>8<\/td><td>1000<\/td><td>10<\/td><td>8<\/td><\/tr>\r\n <tr><td>9<\/td><td>1001<\/td><td>11<\/td><td>9<\/td><\/tr>\r\n <tr><td>10<\/td><td>1010<\/td><td>12<\/td><td>A<\/td><\/tr>\r\n <tr><td>11<\/td><td>1011<\/td><td>13<\/td><td>B<\/td><\/tr>\r\n <tr><td>12<\/td><td>1100<\/td><td>14<\/td><td>C<\/td><\/tr>\r\n <tr><td>13<\/td><td>1101<\/td><td>15<\/td><td>D<\/td><\/tr>\r\n <tr><td>14<\/td><td>1110<\/td><td>16<\/td><td>E<\/td><\/tr>\r\n <tr><td>15<\/td><td>1111<\/td><td>17<\/td><td>F<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Binary Codes<\/h3>\r\n\r\n <p><strong>1. Binary Coded Decimal (BCD)<\/strong><\/p>\r\n <p>BCD represents each decimal digit (0-9) using 4 binary bits. Also called 8421 code.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Convert (579)\u2081\u2080 to BCD<\/span>\r\n\r\n5 = 0101\r\n7 = 0111\r\n9 = 1001\r\n\r\n(579)\u2081\u2080 = 0101 0111 1001 (BCD)\r\n<\/pre><\/div>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>BCD (8421)<\/th><th>Binary<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0000<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>0001<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>0101<\/td><\/tr>\r\n <tr><td>9<\/td><td>1001<\/td><td>1001<\/td><\/tr>\r\n <tr><td>12<\/td><td>0001 0010<\/td><td>1100<\/td><\/tr>\r\n <tr><td>25<\/td><td>0010 0101<\/td><td>11001<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>BCD vs Pure Binary:<\/strong> BCD uses more bits but makes decimal-to-binary conversion easier for human-readable displays (like calculators and digital clocks).<\/div>\r\n\r\n <p><strong>2. Gray Code (Reflected Binary Code)<\/strong><\/p>\r\n <p>A binary code where two successive values differ by only one bit. Used in rotary encoders, error correction, and analog-to-digital converters.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Decimal<\/th><th>Binary<\/th><th>Gray Code<\/th><th>Bits Changed<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0000<\/td><td>0000<\/td><td>-<\/td><\/tr>\r\n <tr><td>1<\/td><td>0001<\/td><td>0001<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>2<\/td><td>0010<\/td><td>0011<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>3<\/td><td>0011<\/td><td>0010<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>4<\/td><td>0100<\/td><td>0110<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>5<\/td><td>0101<\/td><td>0111<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>6<\/td><td>0110<\/td><td>0101<\/td><td>1 bit<\/td><\/tr>\r\n <tr><td>7<\/td><td>0111<\/td><td>0100<\/td><td>1 bit<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Binary to Gray Code Conversion:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Method: MSB stays same, then XOR each adjacent pair<\/span>\r\n\r\nBinary: 1 0 1 1\r\n \u2193 \u2295 \u2295 \u2295\r\nGray: 1 1 1 0\r\n\r\n<span class=\"cm\">Step by step:<\/span>\r\nG\u2083 = B\u2083 = 1\r\nG\u2082 = B\u2083 \u2295 B\u2082 = 1 \u2295 0 = 1\r\nG\u2081 = B\u2082 \u2295 B\u2081 = 0 \u2295 1 = 1\r\nG\u2080 = B\u2081 \u2295 B\u2080 = 1 \u2295 1 = 0\r\n<\/pre><\/div>\r\n\r\n <p><strong>Gray to Binary Conversion:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Method: MSB stays same, then XOR with previous binary bit<\/span>\r\n\r\nGray: 1 1 1 0\r\n \u2193 \u2295 \u2295 \u2295\r\nBinary: 1 0 1 1\r\n\r\n<span class=\"cm\">Step by step:<\/span>\r\nB\u2083 = G\u2083 = 1\r\nB\u2082 = B\u2083 \u2295 G\u2082 = 1 \u2295 1 = 0\r\nB\u2081 = B\u2082 \u2295 G\u2081 = 0 \u2295 1 = 1\r\nB\u2080 = B\u2081 \u2295 G\u2080 = 1 \u2295 0 = 1\r\n<\/pre><\/div>\r\n\r\n <h3>ASCII Code (American Standard Code for Information Interchange)<\/h3>\r\n <p>A 7-bit code (128 characters) used to represent text in computers. Extended ASCII uses 8 bits (256 characters).<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Character<\/th><th>Decimal<\/th><th>Binary<\/th><th>Hexadecimal<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>A<\/td><td>65<\/td><td>01000001<\/td><td>41<\/td><\/tr>\r\n <tr><td>B<\/td><td>66<\/td><td>01000010<\/td><td>42<\/td><\/tr>\r\n <tr><td>Z<\/td><td>90<\/td><td>01011010<\/td><td>5A<\/td><\/tr>\r\n <tr><td>a<\/td><td>97<\/td><td>01100001<\/td><td>61<\/td><\/tr>\r\n <tr><td>b<\/td><td>98<\/td><td>01100010<\/td><td>62<\/td><\/tr>\r\n <tr><td>0<\/td><td>48<\/td><td>00110000<\/td><td>30<\/td><\/tr>\r\n <tr><td>1<\/td><td>49<\/td><td>00110001<\/td><td>31<\/td><\/tr>\r\n <tr><td>Space<\/td><td>32<\/td><td>00100000<\/td><td>20<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>ASCII Ranges:<\/strong><\/p>\r\n <ul>\r\n <li><strong>0-31:<\/strong> Control characters (non-printable)<\/li>\r\n <li><strong>32-47:<\/strong> Special characters and space<\/li>\r\n <li><strong>48-57:<\/strong> Digits 0-9<\/li>\r\n <li><strong>65-90:<\/strong> Uppercase letters A-Z<\/li>\r\n <li><strong>97-122:<\/strong> Lowercase letters a-z<\/li>\r\n <\/ul>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Quick Tip:<\/strong> To convert uppercase to lowercase in ASCII, add 32. To convert lowercase to uppercase, subtract 32. Example: 'A' (65) + 32 = 'a' (97)<\/div>\r\n\r\n <h3>Signed Number Representation<\/h3>\r\n\r\n <p><strong>1. Sign-Magnitude<\/strong><\/p>\r\n <p>MSB indicates sign (0=positive, 1=negative). Remaining bits represent magnitude.<\/p>\r\n <div class=\"code-block\"><pre>\r\n+5 = 0101 (MSB=0 means positive)\r\n-5 = 1101 (MSB=1 means negative)\r\n\r\n<span class=\"cm\">Problem: Two representations of zero (+0 and -0)<\/span>\r\n+0 = 0000\r\n-0 = 1000\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. 1's Complement<\/strong><\/p>\r\n <p>Positive numbers: normal binary. Negative numbers: invert all bits.<\/p>\r\n <div class=\"code-block\"><pre>\r\n+5 = 0101\r\n-5 = 1010 (invert all bits of +5)\r\n\r\n+7 = 0111\r\n-7 = 1000 (invert all bits of +7)\r\n\r\n<span class=\"cm\">Problem: Still has two zeros<\/span>\r\n+0 = 0000\r\n-0 = 1111\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. 2's Complement (Most Common)<\/strong><\/p>\r\n <p>Positive numbers: normal binary. Negative numbers: invert all bits and add 1.<\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Find 2's complement of +5<\/span>\r\n\r\n+5 = 0101\r\nInvert: 1010\r\nAdd 1: 1011\r\n-5 = 1011\r\n\r\n<span class=\"cm\">Example: Find 2's complement of +7<\/span>\r\n+7 = 0111\r\nInvert: 1000\r\nAdd 1: 1001\r\n-7 = 1001\r\n\r\n<span class=\"cm\">Advantage: Only one representation of zero<\/span>\r\n+0 = 0000\r\n<\/pre><\/div>\r\n\r\n <p><strong>2's Complement Range for n bits:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Range:<\/strong> -2<sup>n-1<\/sup> to +2<sup>n-1<\/sup>-1<\/li>\r\n <li><strong>4-bit:<\/strong> -8 to +7<\/li>\r\n <li><strong>8-bit:<\/strong> -128 to +127<\/li>\r\n <li><strong>16-bit:<\/strong> -32,768 to +32,767<\/li>\r\n <\/ul>\r\n\r\n <h3>Binary Arithmetic<\/h3>\r\n\r\n <p><strong>Binary Addition Rules:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 0 + 0 = 0\r\n 0 + 1 = 1\r\n 1 + 0 = 1\r\n 1 + 1 = 10 (0 with carry 1)\r\n1 + 1 + 1 = 11 (1 with carry 1)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: 1011 + 1101<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n \u2081\u2081\u2081 (carries)\r\n 1011 (11 in decimal)\r\n + 1101 (13 in decimal)\r\n ------\r\n 11000 (24 in decimal)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Binary Subtraction Rules:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 0 - 0 = 0\r\n 1 - 0 = 1\r\n 1 - 1 = 0\r\n 0 - 1 = 1 (with borrow 1)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: 1101 - 1011<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n 1101 (13 in decimal)\r\n - 1011 (11 in decimal)\r\n ------\r\n 0010 (2 in decimal)\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Convert (11010110)\u2082 to Decimal, Octal, and Hexadecimal. 2) Convert (456)\u2081\u2080 to Binary, Octal, and Hexadecimal. 3) Convert (3F7)\u2081\u2086 to Binary. 4) Find 2's complement of (01101)\u2082. 5) Add (1011)\u2082 + (1110)\u2082<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-2\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 2<\/span>\r\n <h2>Boolean Algebra<\/h2>\r\n <p>Laws, theorems, De Morgan's rules, simplification techniques and truth tables<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is Boolean Algebra?<\/h3>\r\n <p><strong>Boolean Algebra<\/strong> is a branch of algebra that deals with binary variables and logical operations. Developed by <strong>George Boole<\/strong> in 1854, it forms the foundation of digital logic design.<\/p>\r\n\r\n <p><strong>Boolean Variables:<\/strong> Can have only two values: <strong>0 (False)<\/strong> or <strong>1 (True)<\/strong><\/p>\r\n\r\n <h3>Basic Boolean Operations<\/h3>\r\n\r\n <p><strong>1. AND Operation (\u00b7)<\/strong><\/p>\r\n <p>Output is 1 only when ALL inputs are 1. Symbol: \u00b7 or \u2227<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A \u00b7 B or Z = A AND B or Z = AB\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Z=A\u00b7B\r\n0 0 | 0\r\n0 1 | 0\r\n1 0 | 0\r\n1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. OR Operation (+)<\/strong><\/p>\r\n <p>Output is 1 when AT LEAST ONE input is 1. Symbol: + or \u2228<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A + B or Z = A OR B\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Z=A+B\r\n0 0 | 0\r\n0 1 | 1\r\n1 0 | 1\r\n1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. NOT Operation (')<\/strong><\/p>\r\n <p>Output is the complement\/inverse of input. Symbol: ' or \u00ac or \u203e<\/p>\r\n <div class=\"code-block\"><pre>\r\nZ = A' or Z = NOT A or Z = \u0100\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA | Z=A'\r\n0 | 1\r\n1 | 0\r\n<\/pre><\/div>\r\n\r\n <h3>Boolean Algebra Laws<\/h3>\r\n\r\n <p><strong>1. Identity Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Identity<\/div>\r\n <div class=\"concept-rule\">A + 0 = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Identity<\/div>\r\n <div class=\"concept-rule\">A \u00b7 1 = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>2. Null (Dominance) Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Null<\/div>\r\n <div class=\"concept-rule\">A + 1 = 1<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Null<\/div>\r\n <div class=\"concept-rule\">A \u00b7 0 = 0<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>3. Idempotent Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Idempotent<\/div>\r\n <div class=\"concept-rule\">A + A = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Idempotent<\/div>\r\n <div class=\"concept-rule\">A \u00b7 A = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>4. Complement Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Complement<\/div>\r\n <div class=\"concept-rule\">A + A' = 1<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Complement<\/div>\r\n <div class=\"concept-rule\">A \u00b7 A' = 0<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Double Negation<\/div>\r\n <div class=\"concept-rule\">(A')' = A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>5. Commutative Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Commutative<\/div>\r\n <div class=\"concept-rule\">A + B = B + A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Commutative<\/div>\r\n <div class=\"concept-rule\">A \u00b7 B = B \u00b7 A<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>6. Associative Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR Associative<\/div>\r\n <div class=\"concept-rule\">A+(B+C) = (A+B)+C<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND Associative<\/div>\r\n <div class=\"concept-rule\">A\u00b7(B\u00b7C) = (A\u00b7B)\u00b7C<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>7. Distributive Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">AND over OR<\/div>\r\n <div class=\"concept-rule\">A\u00b7(B+C) = A\u00b7B + A\u00b7C<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">OR over AND<\/div>\r\n <div class=\"concept-rule\">A+(B\u00b7C) = (A+B)\u00b7(A+C)<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <p><strong>8. Absorption Laws<\/strong><\/p>\r\n <div class=\"concept-grid\">\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 1<\/div>\r\n <div class=\"concept-rule\">A + A\u00b7B = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 2<\/div>\r\n <div class=\"concept-rule\">A \u00b7 (A+B) = A<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 3<\/div>\r\n <div class=\"concept-rule\">A + A'\u00b7B = A + B<\/div>\r\n <\/div>\r\n <div class=\"concept-card\">\r\n <div class=\"concept-name\">Absorption 4<\/div>\r\n <div class=\"concept-rule\">A \u00b7 (A'+B) = A \u00b7 B<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n <h3>De Morgan's Theorems<\/h3>\r\n <p><strong>De Morgan's Laws<\/strong> are fundamental theorems for complementing Boolean expressions:<\/p>\r\n\r\n <p><strong>Theorem 1:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A + B)' = A' \u00b7 B'\r\n\r\n<span class=\"cm\">The complement of OR equals AND of complements<\/span>\r\n\r\n<span class=\"cm\">Proof by Truth Table:<\/span>\r\nA B | A+B (A+B)' | A' B' A'\u00b7B'\r\n0 0 | 0 1 | 1 1 1 \u2713\r\n0 1 | 1 0 | 1 0 0 \u2713\r\n1 0 | 1 0 | 0 1 0 \u2713\r\n1 1 | 1 0 | 0 0 0 \u2713\r\n<\/pre><\/div>\r\n\r\n <p><strong>Theorem 2:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A \u00b7 B)' = A' + B'\r\n\r\n<span class=\"cm\">The complement of AND equals OR of complements<\/span>\r\n\r\n<span class=\"cm\">Proof by Truth Table:<\/span>\r\nA B | A\u00b7B (A\u00b7B)' | A' B' A'+B'\r\n0 0 | 0 1 | 1 1 1 \u2713\r\n0 1 | 0 1 | 1 0 1 \u2713\r\n1 0 | 0 1 | 0 1 1 \u2713\r\n1 1 | 1 0 | 0 0 0 \u2713\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>De Morgan's Quick Rule:<\/strong> Break the bar, change the operation (+ to \u00b7, or \u00b7 to +)<\/div>\r\n\r\n <p><strong>Extended De Morgan's:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A + B + C)' = A' \u00b7 B' \u00b7 C'\r\n\r\n(A \u00b7 B \u00b7 C)' = A' + B' + C'\r\n\r\n(A + B\u00b7C)' = A' \u00b7 (B'+C')\r\n\r\n(A\u00b7B + C\u00b7D)' = (A'+B') \u00b7 (C'+D')\r\n<\/pre><\/div>\r\n\r\n <h3>Boolean Expression Simplification<\/h3>\r\n\r\n <p><strong>Example 1: Simplify A\u00b7B + A\u00b7B'<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA\u00b7B + A\u00b7B'\r\n= A\u00b7(B + B') <span class=\"cm\">Distributive law<\/span>\r\n= A\u00b71 <span class=\"cm\">Complement law: B+B'=1<\/span>\r\n= A <span class=\"cm\">Identity law: A\u00b71=A<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 2: Simplify (A+B)\u00b7(A+B')<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n(A+B)\u00b7(A+B')\r\n= A + B\u00b7B' <span class=\"cm\">Distributive law<\/span>\r\n= A + 0 <span class=\"cm\">Complement law: B\u00b7B'=0<\/span>\r\n= A <span class=\"cm\">Identity law: A+0=A<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 3: Simplify A + A\u00b7B<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA + A\u00b7B\r\n= A\u00b71 + A\u00b7B <span class=\"cm\">Identity law: A=A\u00b71<\/span>\r\n= A\u00b7(1 + B) <span class=\"cm\">Distributive law<\/span>\r\n= A\u00b71 <span class=\"cm\">Null law: 1+B=1<\/span>\r\n= A <span class=\"cm\">Identity law<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example 4: Simplify A'\u00b7B\u00b7C + A\u00b7B\u00b7C + A\u00b7B\u00b7C'<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nA'\u00b7B\u00b7C + A\u00b7B\u00b7C + A\u00b7B\u00b7C'\r\n= B\u00b7C\u00b7(A'+A) + A\u00b7B\u00b7C' <span class=\"cm\">Factor out B\u00b7C<\/span>\r\n= B\u00b7C\u00b71 + A\u00b7B\u00b7C' <span class=\"cm\">Complement law<\/span>\r\n= B\u00b7C + A\u00b7B\u00b7C' <span class=\"cm\">Identity law<\/span>\r\n= B\u00b7(C + A\u00b7C') <span class=\"cm\">Factor out B<\/span>\r\n= B\u00b7(C + A) <span class=\"cm\">Absorption law<\/span>\r\n= A\u00b7B + B\u00b7C <span class=\"cm\">Distributive law<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Standard Forms of Boolean Expressions<\/h3>\r\n\r\n <p><strong>1. Sum of Products (SOP)<\/strong><\/p>\r\n <p>OR of AND terms. Each AND term is called a <strong>minterm<\/strong>.<\/p>\r\n <div class=\"code-block\"><pre>\r\nF = A'\u00b7B\u00b7C + A\u00b7B'\u00b7C + A\u00b7B\u00b7C'\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,7)<\/span>\r\nF = A'\u00b7B'\u00b7C + A'\u00b7B\u00b7C + A\u00b7B'\u00b7C + A\u00b7B\u00b7C\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Product of Sums (POS)<\/strong><\/p>\r\n <p>AND of OR terms. Each OR term is called a <strong>maxterm<\/strong>.<\/p>\r\n <div class=\"code-block\"><pre>\r\nF = (A+B+C)\u00b7(A+B'+C)\u00b7(A'+B+C')\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a0M(0,2,4,6)<\/span>\r\nF = (A+B+C)\u00b7(A+B+C')\u00b7(A+B'+C)\u00b7(A+B'+C')\r\n<\/pre><\/div>\r\n\r\n <h3>Truth Table to Boolean Expression<\/h3>\r\n\r\n <p><strong>Example: Create expression from truth table<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B C | F\r\n0 0 0 | 0\r\n0 0 1 | 1 \u2190 m\u2081 = A'\u00b7B'\u00b7C\r\n0 1 0 | 0\r\n0 1 1 | 1 \u2190 m\u2083 = A'\u00b7B\u00b7C\r\n1 0 0 | 1 \u2190 m\u2084 = A\u00b7B'\u00b7C'\r\n1 0 1 | 0\r\n1 1 0 | 1 \u2190 m\u2086 = A\u00b7B\u00b7C'\r\n1 1 1 | 0\r\n\r\n<span class=\"cm\">SOP Form (use rows where F=1):<\/span>\r\nF = A'\u00b7B'\u00b7C + A'\u00b7B\u00b7C + A\u00b7B'\u00b7C' + A\u00b7B\u00b7C'\r\n\r\n<span class=\"cm\">Simplified:<\/span>\r\nF = A'\u00b7C\u00b7(B'+B) + A\u00b7C'\u00b7(B'+B)\r\nF = A'\u00b7C + A\u00b7C'\r\n<\/pre><\/div>\r\n\r\n <h3>Canonical Forms<\/h3>\r\n\r\n <p><strong>Minterms (m):<\/strong> Product terms with all variables present (in normal or complement form)<\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Row<\/th><th>A B C<\/th><th>Minterm<\/th><th>Notation<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0 0 0<\/td><td>A'\u00b7B'\u00b7C'<\/td><td>m\u2080<\/td><\/tr>\r\n <tr><td>1<\/td><td>0 0 1<\/td><td>A'\u00b7B'\u00b7C<\/td><td>m\u2081<\/td><\/tr>\r\n <tr><td>2<\/td><td>0 1 0<\/td><td>A'\u00b7B\u00b7C'<\/td><td>m\u2082<\/td><\/tr>\r\n <tr><td>3<\/td><td>0 1 1<\/td><td>A'\u00b7B\u00b7C<\/td><td>m\u2083<\/td><\/tr>\r\n <tr><td>4<\/td><td>1 0 0<\/td><td>A\u00b7B'\u00b7C'<\/td><td>m\u2084<\/td><\/tr>\r\n <tr><td>5<\/td><td>1 0 1<\/td><td>A\u00b7B'\u00b7C<\/td><td>m\u2085<\/td><\/tr>\r\n <tr><td>6<\/td><td>1 1 0<\/td><td>A\u00b7B\u00b7C'<\/td><td>m\u2086<\/td><\/tr>\r\n <tr><td>7<\/td><td>1 1 1<\/td><td>A\u00b7B\u00b7C<\/td><td>m\u2087<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Maxterms (M):<\/strong> Sum terms with all variables present<\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Row<\/th><th>A B C<\/th><th>Maxterm<\/th><th>Notation<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>0<\/td><td>0 0 0<\/td><td>A+B+C<\/td><td>M\u2080<\/td><\/tr>\r\n <tr><td>1<\/td><td>0 0 1<\/td><td>A+B+C'<\/td><td>M\u2081<\/td><\/tr>\r\n <tr><td>2<\/td><td>0 1 0<\/td><td>A+B'+C<\/td><td>M\u2082<\/td><\/tr>\r\n <tr><td>3<\/td><td>0 1 1<\/td><td>A+B'+C'<\/td><td>M\u2083<\/td><\/tr>\r\n <tr><td>4<\/td><td>1 0 0<\/td><td>A'+B+C<\/td><td>M\u2084<\/td><\/tr>\r\n <tr><td>5<\/td><td>1 0 1<\/td><td>A'+B+C'<\/td><td>M\u2085<\/td><\/tr>\r\n <tr><td>6<\/td><td>1 1 0<\/td><td>A'+B'+C<\/td><td>M\u2086<\/td><\/tr>\r\n <tr><td>7<\/td><td>1 1 1<\/td><td>A'+B'+C'<\/td><td>M\u2087<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Quick Conversion:<\/strong> SOP to POS: F(A,B,C) = \u03a3m(1,3,5,7) = \u03a0M(0,2,4,6). Use rows NOT in minterm list for maxterm list.<\/div>\r\n\r\n <h3>Consensus Theorem<\/h3>\r\n <div class=\"code-block\"><pre>\r\nA\u00b7B + A'\u00b7C + B\u00b7C = A\u00b7B + A'\u00b7C\r\n\r\n<span class=\"cm\">The term B\u00b7C is redundant (consensus term)<\/span>\r\n\r\n<span class=\"cm\">Dual form:<\/span>\r\n(A+B)\u00b7(A'+C)\u00b7(B+C) = (A+B)\u00b7(A'+C)\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Simplify: A\u00b7B + A'\u00b7C + B\u00b7C 2) Apply De Morgan's: (A+B\u00b7C)' 3) Convert to SOP: F(A,B,C) with F=1 for rows 1,2,4,7 4) Prove: A+A\u00b7B = A using Boolean laws 5) Simplify: (A+B)\u00b7(A'+B)\u00b7(A+B')<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-3\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 3<\/span>\r\n <h2>Logic Gates<\/h2>\r\n <p>AND, OR, NOT, NAND, NOR, XOR, XNOR gates with symbols, truth tables, and diagrams<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Logic Gate?<\/h3>\r\n <p>A <strong>logic gate<\/strong> is a basic building block of digital circuits. It performs a logical operation on one or more binary inputs and produces a single binary output.<\/p>\r\n\r\n <div class=\"feature-grid\">\r\n <div class=\"feature-item\">\ud83d\udd0c Basic Gates: AND, OR, NOT<\/div>\r\n <div class=\"feature-item\">\u26a1 Universal Gates: NAND, NOR<\/div>\r\n <div class=\"feature-item\">\ud83d\udd04 Special Gates: XOR, XNOR<\/div>\r\n <div class=\"feature-item\">\ud83d\udca1 Used in CPUs, Memory, ALUs<\/div>\r\n <\/div>\r\n\r\n <h3>1. AND Gate<\/h3>\r\n <p>Output is HIGH (1) only when ALL inputs are HIGH.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502\u2572\r\n \u2502 \u2572\r\n \u2502 \u251c\u2500\u2500\u2500 Y = A\u00b7B\r\n \u2502 \u2571\r\n \u2502\u2571\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A \u00b7 B or Y = AB\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A\u00b7B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Enable\/disable signals, multiplication in ALU, conditional operations<\/p>\r\n\r\n <h3>2. OR Gate<\/h3>\r\n <p>Output is HIGH when AT LEAST ONE input is HIGH.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502)\r\n \u2502 )\r\n \u2502 \u251c\u2500\u2500\u2500 Y = A+B\r\n \u2502 )\r\n \u2502)\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A + B\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A+B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Combining multiple enable signals, addition in ALU, error detection<\/p>\r\n\r\n <h3>3. NOT Gate (Inverter)<\/h3>\r\n <p>Output is the inverse of input. Single input gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u25b7\u25cb\u2500\u2500\u2500 Y = A'\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A' or Y = \u0100\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 Y=A' \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Inverting signals, creating complement, clock signal inversion<\/p>\r\n\r\n <h3>4. NAND Gate (NOT-AND)<\/h3>\r\n <p>Output is LOW only when ALL inputs are HIGH. Complement of AND gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502\u2572\r\n \u2502 \u2572\r\n \u2502 \u251c\u25cb\u2500\u2500\u2500 Y = (A\u00b7B)'\r\n \u2502 \u2571\r\n \u2502\u2571\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A \u00b7 B)' or Y = A\u0305\u00b7\u0305B\u0305\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A\u00b7B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Universal Gate:<\/strong> NAND gate can implement ANY logic function (AND, OR, NOT, etc.). It's the most commonly used gate in IC fabrication.<\/div>\r\n\r\n <h3>5. NOR Gate (NOT-OR)<\/h3>\r\n <p>Output is HIGH only when ALL inputs are LOW. Complement of OR gate.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n \u2502)\r\n \u2502 )\r\n \u2502 \u251c\u25cb\u2500\u2500\u2500 Y = (A+B)'\r\n \u2502 )\r\n \u2502)\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A + B)' or Y = A\u0305+\u0305B\u0305\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A+B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Universal Gate:<\/strong> NOR gate can also implement ANY logic function. Both NAND and NOR are universal gates.<\/div>\r\n\r\n <h3>6. XOR Gate (Exclusive-OR)<\/h3>\r\n <p>Output is HIGH when inputs are DIFFERENT.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n ))\r\n ) )\r\n ) \u251c\u2500\u2500\u2500 Y = A\u2295B\r\n ) )\r\n ))\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = A \u2295 B = A'\u00b7B + A\u00b7B'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=A\u2295B \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502\r\n\u2502 0 \u2502 1 \u2502 1 \u2502\r\n\u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 1 \u2502 1 \u2502 0 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Addition circuits (Half Adder, Full Adder), parity checkers, data encryption<\/p>\r\n\r\n <h3>7. XNOR Gate (Exclusive-NOR)<\/h3>\r\n <p>Output is HIGH when inputs are SAME. Complement of XOR.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n ))\r\n ) )\r\n ) \u251c\u25cb\u2500\u2500\u2500 Y = (A\u2295B)'\r\n ) )\r\n ))\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span> Y = (A \u2295 B)' = A\u00b7B + A'\u00b7B'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 Y=(A\u2295B)'\u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Equality checker, comparators, error detection<\/p>\r\n\r\n <h3>Summary of All Gates<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Gate<\/th><th>Expression<\/th><th>Output 1 when<\/th><th>Type<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>AND<\/td><td>A\u00b7B<\/td><td>ALL inputs are 1<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>OR<\/td><td>A+B<\/td><td>AT LEAST ONE input is 1<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>NOT<\/td><td>A'<\/td><td>Input is 0<\/td><td>Basic<\/td><\/tr>\r\n <tr><td>NAND<\/td><td>(A\u00b7B)'<\/td><td>AT LEAST ONE input is 0<\/td><td>Universal<\/td><\/tr>\r\n <tr><td>NOR<\/td><td>(A+B)'<\/td><td>ALL inputs are 0<\/td><td>Universal<\/td><\/tr>\r\n <tr><td>XOR<\/td><td>A\u2295B<\/td><td>Inputs are DIFFERENT<\/td><td>Special<\/td><\/tr>\r\n <tr><td>XNOR<\/td><td>(A\u2295B)'<\/td><td>Inputs are SAME<\/td><td>Special<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Complete Truth Table Comparison<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n\u250c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n\u2502 A \u2502 B \u2502 AND \u2502 OR \u2502 NOT \u2502 NAND \u2502 NOR \u2502 XOR \u2502 XNOR \u2502\r\n\u251c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2524\r\n\u2502 0 \u2502 0 \u2502 0 \u2502 0 \u2502 1,0 \u2502 1 \u2502 1 \u2502 0 \u2502 1 \u2502\r\n\u2502 0 \u2502 1 \u2502 0 \u2502 1 \u2502 1,0 \u2502 1 \u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 0 \u2502 0 \u2502 1 \u2502 0,1 \u2502 1 \u2502 0 \u2502 1 \u2502 0 \u2502\r\n\u2502 1 \u2502 1 \u2502 1 \u2502 1 \u2502 0,1 \u2502 0 \u2502 0 \u2502 0 \u2502 1 \u2502\r\n\u2514\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Implementing Gates Using NAND<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. NOT using NAND:<\/span>\r\n A \u2500\u2500\u2500\u2500NAND\u2500\u2500\u2500\u2500 A' (Connect both inputs together)\r\n \u2502\r\n A \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">2. AND using NAND:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n NAND\u2500\u2500NAND\u2500\u2500 A\u00b7B\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">3. OR using NAND:<\/span>\r\n A \u2500\u2500NAND\u2500\u2500\u2510\r\n NAND\u2500\u2500 A+B\r\n B \u2500\u2500NAND\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">4. NOR using NAND:<\/span>\r\n A \u2500\u2500NAND\u2500\u2500\u2510\r\n NAND\u2500\u2500NAND\u2500\u2500 (A+B)'\r\n B \u2500\u2500NAND\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Implementing Gates Using NOR<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. NOT using NOR:<\/span>\r\n A \u2500\u2500\u2500\u2500NOR\u2500\u2500\u2500\u2500 A' (Connect both inputs together)\r\n \u2502\r\n A \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">2. OR using NOR:<\/span>\r\n A \u2500\u2500\u2500\u2500\u2510\r\n NOR\u2500\u2500NOR\u2500\u2500 A+B\r\n B \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">3. AND using NOR:<\/span>\r\n A \u2500\u2500NOR\u2500\u2500\u2510\r\n NOR\u2500\u2500 A\u00b7B\r\n B \u2500\u2500NOR\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">4. NAND using NOR:<\/span>\r\n A \u2500\u2500NOR\u2500\u2500\u2510\r\n NOR\u2500\u2500NOR\u2500\u2500 (A\u00b7B)'\r\n B \u2500\u2500NOR\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>Multiple-Input Gates<\/h3>\r\n\r\n <p><strong>3-Input AND Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A\u00b7B\u00b7C<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0\r\n0 0 1 | 0\r\n0 1 0 | 0\r\n0 1 1 | 0\r\n1 0 0 | 0\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1 \u2190 Only when ALL are 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Input OR Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A+B+C<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0 \u2190 Only when ALL are 0\r\n0 0 1 | 1\r\n0 1 0 | 1\r\n0 1 1 | 1\r\n1 0 0 | 1\r\n1 0 1 | 1\r\n1 1 0 | 1\r\n1 1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Input XOR Gate:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Y = A\u2295B\u2295C (Output 1 when ODD number of 1s)<\/span>\r\n\r\nA B C | Y\r\n0 0 0 | 0\r\n0 0 1 | 1 \u2190 Odd (1)\r\n0 1 0 | 1 \u2190 Odd (1)\r\n0 1 1 | 0\r\n1 0 0 | 1 \u2190 Odd (1)\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1 \u2190 Odd (3)\r\n<\/pre><\/div>\r\n\r\n <h3>Tri-State Buffer<\/h3>\r\n <p>A special gate with 3 output states: HIGH (1), LOW (0), and HIGH-IMPEDANCE (Z - disconnected).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\n Data \u2500\u2500\u2500\u2500\u25b7\u2500\u2500\u2500\u2500 Output\r\n \u2502\r\n Enable\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEnable Data | Output\r\n 0 X | Z (High-impedance, disconnected)\r\n 1 0 | 0\r\n 1 1 | 1\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Bus systems, memory interfacing, bidirectional data lines<\/p>\r\n\r\n <h3>Logic Gate IC Packages<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Gate Type<\/th><th>Description<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>7400<\/td><td>NAND<\/td><td>Quad 2-input NAND gates<\/td><\/tr>\r\n <tr><td>7402<\/td><td>NOR<\/td><td>Quad 2-input NOR gates<\/td><\/tr>\r\n <tr><td>7404<\/td><td>NOT<\/td><td>Hex inverters<\/td><\/tr>\r\n <tr><td>7408<\/td><td>AND<\/td><td>Quad 2-input AND gates<\/td><\/tr>\r\n <tr><td>7432<\/td><td>OR<\/td><td>Quad 2-input OR gates<\/td><\/tr>\r\n <tr><td>7486<\/td><td>XOR<\/td><td>Quad 2-input XOR gates<\/td><\/tr>\r\n <tr><td>74266<\/td><td>XNOR<\/td><td>Quad 2-input XNOR gates<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Draw logic circuit for: Y = A\u00b7B + B\u00b7C' 2) Create truth table for 3-input NAND gate 3) Implement OR gate using only NAND gates 4) Find output of XOR gate when A=1, B=0 5) What is the output of: (A NAND B) OR (C XOR D) for A=1, B=1, C=0, D=1?<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-4\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 4<\/span>\r\n <h2>Combinational Circuits<\/h2>\r\n <p>Adders, Subtractors, Multiplexers, Demultiplexers, Encoders, Decoders, Comparators<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What are Combinational Circuits?<\/h3>\r\n <p><strong>Combinational circuits<\/strong> are logic circuits whose outputs depend ONLY on present inputs (no memory). Output changes immediately when input changes.<\/p>\r\n\r\n <p><strong>Characteristics:<\/strong><\/p>\r\n <ul>\r\n <li>No feedback loops<\/li>\r\n <li>No memory elements (no flip-flops)<\/li>\r\n <li>Output = f(present inputs only)<\/li>\r\n <li>Faster than sequential circuits<\/li>\r\n <\/ul>\r\n\r\n <h3>1. Half Adder<\/h3>\r\n <p>Adds two 1-bit binary numbers. Produces SUM and CARRY.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Sum Carry\r\n0 0 | 0 0\r\n0 1 | 1 0\r\n1 0 | 1 0\r\n1 1 | 0 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nSum = A \u2295 B (XOR)\r\nCarry = A \u00b7 B (AND)\r\n\r\n<span class=\"cm\">Circuit Diagram:<\/span>\r\nA \u2500\u2500\u2500\u2510\r\n XOR\u2500\u2500\u2500\u2500 Sum\r\nB \u2500\u2500\u2500\u2518\r\n\r\nA \u2500\u2500\u2500\u2510\r\n AND\u2500\u2500\u2500\u2500 Carry\r\nB \u2500\u2500\u2500\u2518\r\n<\/pre><\/div>\r\n\r\n <h3>2. Full Adder<\/h3>\r\n <p>Adds THREE 1-bit binary numbers (A, B, and Carry-in). Produces SUM and CARRY-out.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B Cin | Sum Cout\r\n0 0 0 | 0 0\r\n0 0 1 | 1 0\r\n0 1 0 | 1 0\r\n0 1 1 | 0 1\r\n1 0 0 | 1 0\r\n1 0 1 | 0 1\r\n1 1 0 | 0 1\r\n1 1 1 | 1 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nSum = A \u2295 B \u2295 Cin\r\nCout = A\u00b7B + Cin\u00b7(A\u2295B)\r\n = A\u00b7B + B\u00b7Cin + A\u00b7Cin\r\n\r\n<span class=\"cm\">Implementation using Two Half Adders:<\/span>\r\nA \u2500\u2500\u2510 \u250c\u2500\u2500\u2500 Sum\r\n HA1 \u2500\u2500 S \u2500\u2500\u2500HA2\r\nB \u2500\u2500\u2518 C \u2502\r\n \u2502 Cin\r\n \u2514\u2500\u2500OR\u2500\u2500\u2518\u2500\u2500\u2500 Cout\r\n<\/pre><\/div>\r\n\r\n <h3>4-bit Binary Adder (Ripple Carry)<\/h3>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Connects 4 Full Adders in series<\/span>\r\n\r\nA\u2083B\u2083 A\u2082B\u2082 A\u2081B\u2081 A\u2080B\u2080\r\n \u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502\r\n FA FA FA FA\r\n \u2502 \u2502 \u2502 \u2502\r\nC\u2084\u2500\u2500\u2500\u2500C\u2083\u2500\u2500\u2500\u2500C\u2082\u2500\u2500\u2500\u2500C\u2081\u2500\u2500\u2500\u2500C\u2080(0)\r\n\r\nSum: S\u2083 S\u2082 S\u2081 S\u2080\r\nCarry: C\u2084\r\n<\/pre><\/div>\r\n\r\n <h3>3. Half Subtractor<\/h3>\r\n <p>Subtracts two 1-bit binary numbers.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | Diff Borrow\r\n0 0 | 0 0\r\n0 1 | 1 1\r\n1 0 | 1 0\r\n1 1 | 0 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nDiff = A \u2295 B\r\nBorrow = A'\u00b7B\r\n<\/pre><\/div>\r\n\r\n <h3>4. Full Subtractor<\/h3>\r\n <p>Subtracts three bits (A - B - Bin).<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nDiff = A \u2295 B \u2295 Bin\r\nBout = A'\u00b7B + Bin\u00b7(A\u2295B)'\r\n = A'\u00b7B + A'\u00b7Bin + B\u00b7Bin\r\n<\/pre><\/div>\r\n\r\n <h3>5. Multiplexer (MUX)<\/h3>\r\n <p>Data selector. Selects ONE of many inputs and forwards it to output based on select lines.<\/p>\r\n\r\n <p><strong>2:1 Multiplexer (2 inputs, 1 select line)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nI\u2080 \u2500\u2500\u2510\r\n \u2502 MUX\r\nI\u2081 \u2500\u2500\u2524 2:1 \u2500\u2500\u2500\u2500 Y\r\n \u2502\r\nS \u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS | Y\r\n0 | I\u2080\r\n1 | I\u2081\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span>\r\nY = S'\u00b7I\u2080 + S\u00b7I\u2081\r\n<\/pre><\/div>\r\n\r\n <p><strong>4:1 Multiplexer (4 inputs, 2 select lines)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nI\u2080 \u2500\u2500\u2510\r\nI\u2081 \u2500\u2500\u2524 MUX\r\nI\u2082 \u2500\u2500\u2524 4:1 \u2500\u2500\u2500\u2500 Y\r\nI\u2083 \u2500\u2500\u2518\r\nS\u2081S\u2080\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS\u2081 S\u2080 | Y\r\n0 0 | I\u2080\r\n0 1 | I\u2081\r\n1 0 | I\u2082\r\n1 1 | I\u2083\r\n\r\n<span class=\"cm\">Boolean Expression:<\/span>\r\nY = S\u2081'\u00b7S\u2080'\u00b7I\u2080 + S\u2081'\u00b7S\u2080\u00b7I\u2081 + S\u2081\u00b7S\u2080'\u00b7I\u2082 + S\u2081\u00b7S\u2080\u00b7I\u2083\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Data routing, parallel-to-serial conversion, function generators, ALU input selection<\/p>\r\n\r\n <h3>6. Demultiplexer (DEMUX)<\/h3>\r\n <p>Data distributor. Routes ONE input to ONE of many outputs based on select lines.<\/p>\r\n\r\n <p><strong>1:4 Demultiplexer<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\n \u250c\u2500\u2500\u2500\u2500 Y\u2080\r\n \u2502\r\n D\u2500\u2500\u2500\u2500\u2524DEMUX Y\u2081\r\n 1:4 \u2502\r\n \u2502\u2500\u2500\u2500\u2500 Y\u2082\r\n \u2502\r\n \u2514\u2500\u2500\u2500\u2500 Y\u2083\r\n S\u2081S\u2080\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS\u2081 S\u2080 | Y\u2080 Y\u2081 Y\u2082 Y\u2083\r\n0 0 | D 0 0 0\r\n0 1 | 0 D 0 0\r\n1 0 | 0 0 D 0\r\n1 1 | 0 0 0 D\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2080 = S\u2081'\u00b7S\u2080'\u00b7D\r\nY\u2081 = S\u2081'\u00b7S\u2080\u00b7D\r\nY\u2082 = S\u2081\u00b7S\u2080'\u00b7D\r\nY\u2083 = S\u2081\u00b7S\u2080\u00b7D\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Serial-to-parallel conversion, address decoding, communication systems<\/p>\r\n\r\n <h3>7. Encoder<\/h3>\r\n <p>Converts 2\u207f input lines to n output lines. Only ONE input should be active at a time.<\/p>\r\n\r\n <p><strong>4:2 Encoder (4 inputs to 2 outputs)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nI\u2083 I\u2082 I\u2081 I\u2080 | Y\u2081 Y\u2080\r\n0 0 0 1 | 0 0\r\n0 0 1 0 | 0 1\r\n0 1 0 0 | 1 0\r\n1 0 0 0 | 1 1\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2081 = I\u2083 + I\u2082\r\nY\u2080 = I\u2083 + I\u2081\r\n<\/pre><\/div>\r\n\r\n <p><strong>Priority Encoder:<\/strong> When multiple inputs are active, encodes the highest priority input.<\/p>\r\n\r\n <p><strong>Applications:<\/strong> Keyboard encoding, interrupt handling, data compression<\/p>\r\n\r\n <h3>8. Decoder<\/h3>\r\n <p>Converts n input lines to 2\u207f output lines. Only ONE output is active for each input combination.<\/p>\r\n\r\n <p><strong>2:4 Decoder (2 inputs to 4 outputs)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA\u2081 A\u2080 | Y\u2083 Y\u2082 Y\u2081 Y\u2080\r\n0 0 | 0 0 0 1\r\n0 1 | 0 0 1 0\r\n1 0 | 0 1 0 0\r\n1 1 | 1 0 0 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nY\u2080 = A\u2081'\u00b7A\u2080'\r\nY\u2081 = A\u2081'\u00b7A\u2080\r\nY\u2082 = A\u2081\u00b7A\u2080'\r\nY\u2083 = A\u2081\u00b7A\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Memory address decoding, instruction decoding, display drivers (7-segment)<\/p>\r\n\r\n <h3>9. 7-Segment Display Decoder<\/h3>\r\n <p>Converts 4-bit BCD to 7-segment display output.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">7-Segment Display Layout:<\/span>\r\n aaa\r\n f b\r\n ggg\r\n e c\r\n ddd\r\n\r\n<span class=\"cm\">BCD to 7-Segment:<\/span>\r\nBCD | abcdefg | Display\r\n0000 | 1111110 | 0\r\n0001 | 0110000 | 1\r\n0010 | 1101101 | 2\r\n0011 | 1111001 | 3\r\n0100 | 0110011 | 4\r\n0101 | 1011011 | 5\r\n0110 | 1011111 | 6\r\n0111 | 1110000 | 7\r\n1000 | 1111111 | 8\r\n1001 | 1111011 | 9\r\n<\/pre><\/div>\r\n\r\n <h3>10. Magnitude Comparator<\/h3>\r\n <p>Compares two binary numbers and indicates whether they are equal, or one is greater\/less than the other.<\/p>\r\n\r\n <p><strong>1-bit Comparator:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table:<\/span>\r\nA B | A>B A=B A<B\r\n0 0 | 0 1 0\r\n0 1 | 0 0 1\r\n1 0 | 1 0 0\r\n1 1 | 0 1 0\r\n\r\n<span class=\"cm\">Boolean Expressions:<\/span>\r\nA > B = A\u00b7B'\r\nA = B = A'\u00b7B' + A\u00b7B = (A\u2295B)'\r\nA < B = A'\u00b7B\r\n<\/pre><\/div>\r\n\r\n <p><strong>2-bit Comparator:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Compare A\u2081A\u2080 with B\u2081B\u2080<\/span>\r\n\r\nA=B when: (A\u2081\u2295B\u2081)' \u00b7 (A\u2080\u2295B\u2080)'\r\n\r\nA>B when: A\u2081\u00b7B\u2081' + (A\u2081\u2295B\u2081)'\u00b7A\u2080\u00b7B\u2080'\r\n\r\nA<B when: A\u2081'\u00b7B\u2081 + (A\u2081\u2295B\u2081)'\u00b7A\u2080'\u00b7B\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Sorting algorithms, control circuits, microprocessor ALU<\/p>\r\n\r\n <h3>Combinational Circuit Design Steps<\/h3>\r\n\r\n <p><strong>Step-by-step Design Process:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Step 1:<\/strong> Problem Statement - Understand what the circuit should do<\/li>\r\n <li><strong>Step 2:<\/strong> Input\/Output Identification - Determine number and type of I\/O<\/li>\r\n <li><strong>Step 3:<\/strong> Truth Table - List all input combinations and desired outputs<\/li>\r\n <li><strong>Step 4:<\/strong> Boolean Expression - Derive from truth table (SOP or POS)<\/li>\r\n <li><strong>Step 5:<\/strong> Simplification - Use Boolean algebra or K-map<\/li>\r\n <li><strong>Step 6:<\/strong> Logic Diagram - Draw circuit using gates<\/li>\r\n <li><strong>Step 7:<\/strong> Verification - Test with all input combinations<\/li>\r\n <\/ul>\r\n\r\n <h3>Parity Generator & Checker<\/h3>\r\n\r\n <p><strong>Even Parity Generator (3-bit):<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Adds parity bit to make total 1s even<\/span>\r\n\r\nA B C | P (Parity bit)\r\n0 0 0 | 0 (0 ones \u2192 even, add 0)\r\n0 0 1 | 1 (1 one \u2192 odd, add 1)\r\n0 1 0 | 1\r\n0 1 1 | 0\r\n1 0 0 | 1\r\n1 0 1 | 0\r\n1 1 0 | 0\r\n1 1 1 | 1\r\n\r\nP = A \u2295 B \u2295 C\r\n<\/pre><\/div>\r\n\r\n <p><strong>Even Parity Checker:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Checks if total 1s (including parity bit) is even<\/span>\r\n\r\nError = A \u2295 B \u2295 C \u2295 P\r\nError = 0 \u2192 No error (even parity maintained)\r\nError = 1 \u2192 Error detected (odd parity)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Error detection in data transmission, memory systems, communication protocols<\/p>\r\n\r\n <h3>Code Converter Circuits<\/h3>\r\n\r\n <p><strong>1. Binary to Gray Code Converter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">For 3-bit (B\u2082B\u2081B\u2080 \u2192 G\u2082G\u2081G\u2080):<\/span>\r\n\r\nG\u2082 = B\u2082\r\nG\u2081 = B\u2082 \u2295 B\u2081\r\nG\u2080 = B\u2081 \u2295 B\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Gray to Binary Code Converter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">For 3-bit (G\u2082G\u2081G\u2080 \u2192 B\u2082B\u2081B\u2080):<\/span>\r\n\r\nB\u2082 = G\u2082\r\nB\u2081 = B\u2082 \u2295 G\u2081\r\nB\u2080 = B\u2081 \u2295 G\u2080\r\n<\/pre><\/div>\r\n\r\n <p><strong>3. BCD to Excess-3 Converter:<\/strong><\/p>\r\n <p>Excess-3 = BCD + 3. Used in arithmetic operations to avoid 0000 representation.<\/p>\r\n\r\n <h3>Arithmetic Logic Unit (ALU)<\/h3>\r\n <p>A combinational circuit that performs arithmetic (add, subtract) and logic (AND, OR, XOR) operations.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Simple 4-function ALU:<\/span>\r\n\r\nInputs: A, B (n-bit data)\r\n S\u2081S\u2080 (2-bit operation select)\r\n\r\nS\u2081 S\u2080 | Operation\r\n0 0 | A AND B\r\n0 1 | A OR B\r\n1 0 | A XOR B\r\n1 1 | A + B\r\n<\/pre><\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Design a half adder and verify with truth table 2) Draw a 4:1 MUX circuit 3) Create truth table for 3:8 decoder 4) Design a 2-bit magnitude comparator 5) Implement full adder using two half adders and an OR gate<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-5\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 5<\/span>\r\n <h2>Sequential Circuits<\/h2>\r\n <p>Flip-flops (SR, JK, D, T), Latches, State diagrams, and Timing diagrams<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What are Sequential Circuits?<\/h3>\r\n <p><strong>Sequential circuits<\/strong> are logic circuits whose outputs depend on BOTH present inputs AND past outputs (memory). They have feedback loops and memory elements.<\/p>\r\n\r\n <p><strong>Combinational vs Sequential:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>Combinational<\/th><th>Sequential<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Memory<\/td><td>No memory<\/td><td>Has memory<\/td><\/tr>\r\n <tr><td>Output depends on<\/td><td>Present inputs only<\/td><td>Present inputs + past state<\/td><\/tr>\r\n <tr><td>Feedback<\/td><td>No feedback<\/td><td>Feedback present<\/td><\/tr>\r\n <tr><td>Clock<\/td><td>Not needed<\/td><td>Usually clock-driven<\/td><\/tr>\r\n <tr><td>Elements<\/td><td>Gates only<\/td><td>Gates + Flip-flops<\/td><\/tr>\r\n <tr><td>Examples<\/td><td>Adder, MUX, Decoder<\/td><td>Counter, Register, FSM<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Types of Sequential Circuits<\/h3>\r\n <ul>\r\n <li><strong>Synchronous:<\/strong> State changes only at clock edges (clock-driven)<\/li>\r\n <li><strong>Asynchronous:<\/strong> State changes immediately when inputs change (no clock)<\/li>\r\n <\/ul>\r\n\r\n <h3>Memory Elements<\/h3>\r\n\r\n <p><strong>1. Latch<\/strong><\/p>\r\n <p>Level-sensitive memory element. Changes output when enable signal is HIGH.<\/p>\r\n\r\n <p><strong>2. Flip-Flop<\/strong><\/p>\r\n <p>Edge-sensitive memory element. Changes output only at clock edge (rising or falling).<\/p>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>Key Difference:<\/strong> Latch is level-triggered (responds to signal level), Flip-flop is edge-triggered (responds to clock edge transition).<\/div>\r\n\r\n <h3>SR Latch (Set-Reset Latch)<\/h3>\r\n <p>Most basic memory element using NAND or NOR gates.<\/p>\r\n\r\n <p><strong>SR Latch using NOR gates:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nS \u2500\u2500NOR\u2500\u2500\u252c\u2500\u2500\u2500\u2500 Q\r\n \u250c\u2500\u2500\u2500\u2500\u2518\r\n \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2510\r\nR \u2500\u2500NOR\u2500\u2500\u2534\u2500\u2500\u2500\u2500 Q'\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nS R | Q Q' | State\r\n0 0 | Q Q' | Hold (No change)\r\n0 1 | 0 1 | Reset\r\n1 0 | 1 0 | Set\r\n1 1 | 0 0 | Invalid (Not allowed!)\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(next) = S + R'\u00b7Q\r\n<\/pre><\/div>\r\n\r\n <div class=\"info-box\">\u26a0\ufe0f <strong>Invalid State:<\/strong> S=R=1 produces Q=Q'=0, violating the rule that Q and Q' should be complements. Avoid this state!<\/div>\r\n\r\n <p><strong>SR Latch using NAND gates:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Truth Table (Active LOW inputs):<\/span>\r\nS\u0304 R\u0304 | Q Q' | State\r\n0 0 | 1 1 | Invalid\r\n0 1 | 1 0 | Set\r\n1 0 | 0 1 | Reset\r\n1 1 | Q Q' | Hold\r\n<\/pre><\/div>\r\n\r\n <h3>Gated SR Latch<\/h3>\r\n <p>SR Latch with enable signal. Changes only when Enable=1.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nS \u2500\u2500\u2510\r\n Enable\u2500\u2500\u2500\u2500 SR Latch \u2500\u2500\u2500\u2500 Q\r\nR \u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500 Q'\r\nEN\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEN S R | Q(next)\r\n0 X X | Q (Hold)\r\n1 0 0 | Q (Hold)\r\n1 0 1 | 0 (Reset)\r\n1 1 0 | 1 (Set)\r\n1 1 1 | Invalid\r\n<\/pre><\/div>\r\n\r\n <h3>D Latch (Data Latch)<\/h3>\r\n <p>Eliminates invalid state of SR latch. Has only one data input.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nD \u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 S\r\n \u2502 SR Latch \u2500\u2500\u2500\u2500 Q\r\n \u2514\u2500\u2500NOT\u2500\u2500 R\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nEN D | Q(next)\r\n0 X | Q (Hold)\r\n1 0 | 0\r\n1 1 | 1\r\n\r\n<span class=\"cm\">When EN=1: Q follows D<\/span>\r\n<span class=\"cm\">When EN=0: Q holds previous value<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Flip-Flops (Edge-Triggered)<\/h3>\r\n\r\n <p><strong>Clock Triggering Types:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Positive Edge Triggered:<\/strong> Changes at rising edge (0\u21921) \u2191<\/li>\r\n <li><strong>Negative Edge Triggered:<\/strong> Changes at falling edge (1\u21920) \u2193<\/li>\r\n <\/ul>\r\n\r\n <h3>1. SR Flip-Flop<\/h3>\r\n <p>Edge-triggered version of SR latch.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nS \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 SR\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\nR \u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table (Positive Edge Triggered):<\/span>\r\nS R | Q(t+1) | Comment\r\n0 0 | Q(t) | No change\r\n0 1 | 0 | Reset\r\n1 0 | 1 | Set\r\n1 1 | Invalid | Not allowed\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = S + R'\u00b7Q(t)\r\n<\/pre><\/div>\r\n\r\n <h3>2. JK Flip-Flop<\/h3>\r\n <p>Most versatile flip-flop. Eliminates invalid state by toggling output when J=K=1.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nJ \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 JK\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\nK \u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nJ K | Q(t+1) | Comment\r\n0 0 | Q(t) | No change (Hold)\r\n0 1 | 0 | Reset\r\n1 0 | 1 | Set\r\n1 1 | Q'(t) | Toggle\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = J\u00b7Q'(t) + K'\u00b7Q(t)\r\n<\/pre><\/div>\r\n\r\n <p><strong>Timing Diagram:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510\r\n \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518\r\nJ \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\r\nK \u2500\u2500\u2510 \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\nQ \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">J=0,K=1 \u2192 Reset (Q=0)<\/span>\r\n<span class=\"cm\">J=1,K=0 \u2192 Set (Q=1)<\/span>\r\n<span class=\"cm\">J=1,K=1 \u2192 Toggle<\/span>\r\n<span class=\"cm\">J=0,K=0 \u2192 Hold<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>3. D Flip-Flop (Data\/Delay Flip-Flop)<\/h3>\r\n <p>Stores one bit of data. Output Q follows input D at clock edge.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nD \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 D\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2514\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nD | Q(t+1)\r\n0 | 0\r\n1 | 1\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = D\r\n\r\n<span class=\"cm\">Note: No invalid state, simplest to use<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Applications:<\/strong> Shift registers, data storage, delay elements, frequency division<\/p>\r\n\r\n <h3>4. T Flip-Flop (Toggle Flip-Flop)<\/h3>\r\n <p>Toggles output when T=1. Used in counters.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Symbol:<\/span>\r\nT \u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 T\r\nCLK \u2500\u2500\u2500\u2524 FF \u2500\u2500\u2500\u2500 Q\r\n \u2502 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2514\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nT | Q(t+1) | Comment\r\n0 | Q(t) | No change\r\n1 | Q'(t) | Toggle\r\n\r\n<span class=\"cm\">Characteristic Equation:<\/span>\r\nQ(t+1) = T\u00b7Q'(t) + T'\u00b7Q(t) = T \u2295 Q(t)\r\n<\/pre><\/div>\r\n\r\n <p><strong>T Flip-Flop from JK:<\/strong> Connect J and K together \u2192 T input<\/p>\r\n <p><strong>T Flip-Flop from D:<\/strong> Feed Q' XOR T to D input<\/p>\r\n\r\n <h3>Flip-Flop Conversion<\/h3>\r\n\r\n <p><strong>Conversion Table:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Convert From<\/th><th>To<\/th><th>Method<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>JK to D<\/td><td>D<\/td><td>D = J = K'<\/td><\/tr>\r\n <tr><td>JK to T<\/td><td>T<\/td><td>J = K = T<\/td><\/tr>\r\n <tr><td>D to JK<\/td><td>JK<\/td><td>J = D, K = D'<\/td><\/tr>\r\n <tr><td>D to T<\/td><td>T<\/td><td>D = T \u2295 Q<\/td><\/tr>\r\n <tr><td>T to JK<\/td><td>JK<\/td><td>J = K = T<\/td><\/tr>\r\n <tr><td>T to D<\/td><td>D<\/td><td>D = T \u2295 Q<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <p><strong>Example: Convert SR to JK<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Excitation Table Comparison:<\/span>\r\n\r\nQ(t) Q(t+1) | S R | J K\r\n 0 0 | 0 X | 0 X\r\n 0 1 | 1 0 | 1 X\r\n 1 0 | 0 1 | X 1\r\n 1 1 | X 0 | X 0\r\n\r\n<span class=\"cm\">Conversion Logic:<\/span>\r\nS = J\u00b7Q'\r\nR = K\u00b7Q\r\n<\/pre><\/div>\r\n\r\n <h3>Master-Slave Flip-Flop<\/h3>\r\n <p>Two flip-flops in series. Master captures input, slave outputs after clock.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Block Diagram:<\/span>\r\nJ \u2500\u2500\u2510 \u250c\u2500\u2500\u2510 \u250c\u2500\u2500 Q\r\n Master FF \u2502 \u2502 Slave FF \u2502\r\nK \u2500\u2500\u2518 Q\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500 Q \u2500\u2500\u2500\u2518\u2500\u2500 Q'\r\nCLK \u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500NOT\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Operation:<\/span>\r\n1. When CLK=1: Master enabled, Slave disabled\r\n Master captures J, K inputs\r\n2. When CLK=0: Master disabled, Slave enabled\r\n Slave copies Master output\r\n\r\n<span class=\"cm\">Advantage: Prevents race conditions<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Preset and Clear Inputs<\/h3>\r\n <p>Asynchronous inputs that override clock. Used for initialization.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Flip-Flop with Preset (PRE) and Clear (CLR):<\/span>\r\n\r\nPRE \u2500\u2500\u2500\u2500\u2510\r\n \u2502 FF\r\nD \u2500\u2500\u2500\u2500\u2524 \u2500\u2500\u2500\u2500 Q\r\nCLK \u2500\u2500\u2500\u2500\u2524 \u2514\u2500\u2500\u2500\u2500 Q'\r\n \u2502\r\nCLR \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Truth Table:<\/span>\r\nPRE CLR | Q Q' | Comment\r\n 0 0 | 1 1 | Invalid\r\n 0 1 | 1 0 | Preset (Set Q=1)\r\n 1 0 | 0 1 | Clear (Set Q=0)\r\n 1 1 | Operates normally with CLK\/D\r\n<\/pre><\/div>\r\n\r\n <h3>State Diagrams<\/h3>\r\n <p>Graphical representation of sequential circuit behavior showing states and transitions.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: 2-bit Binary Counter<\/span>\r\n\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u250c\u2500\u2500\u2502 00 \u2502\u2500\u2500\u2510\r\n \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2518 \u2502\r\n \u2502 \u2193 \u2502\r\n \u2502 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u2502\r\n \u2514\u2500\u2500\u2502 01 \u2502\u2190\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2193\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u250c\u2500\u2500\u2502 10 \u2502\u2190\u2500\u2510\r\n \u2502 \u2514\u2500\u2500\u2500\u2500\u2500\u2518 \u2502\r\n \u2502 \u2193 \u2502\r\n \u2502 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u2502\r\n \u2514\u2500\u2500\u2502 11 \u2502\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2518\r\n \u2193\r\n (back to 00)\r\n\r\n<span class=\"cm\">States: 00 \u2192 01 \u2192 10 \u2192 11 \u2192 00...<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>State Table<\/h3>\r\n <p>Tabular representation of state transitions.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: JK Flip-Flop State Table<\/span>\r\n\r\nPresent Inputs | Next\r\nState J K | State\r\n 0 0 0 | 0\r\n 0 0 1 | 0\r\n 0 1 0 | 1\r\n 0 1 1 | 1\r\n 1 0 0 | 1\r\n 1 0 1 | 0\r\n 1 1 0 | 1\r\n 1 1 1 | 0\r\n<\/pre><\/div>\r\n\r\n <h3>Excitation Tables<\/h3>\r\n <p>Shows required inputs to achieve desired state transitions. Used in flip-flop conversions.<\/p>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Flip-Flop<\/th><th>Q(t)\u2192Q(t+1): 0\u21920<\/th><th>0\u21921<\/th><th>1\u21920<\/th><th>1\u21921<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>SR<\/td><td>S=0, R=X<\/td><td>S=1, R=0<\/td><td>S=0, R=1<\/td><td>S=X, R=0<\/td><\/tr>\r\n <tr><td>JK<\/td><td>J=0, K=X<\/td><td>J=1, K=X<\/td><td>J=X, K=1<\/td><td>J=X, K=0<\/td><\/tr>\r\n <tr><td>D<\/td><td>D=0<\/td><td>D=1<\/td><td>D=0<\/td><td>D=1<\/td><\/tr>\r\n <tr><td>T<\/td><td>T=0<\/td><td>T=1<\/td><td>T=1<\/td><td>T=0<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"info-box\">\ud83d\udca1 <strong>X = Don't Care:<\/strong> Can be 0 or 1, doesn't matter. Used for optimization.<\/div>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Draw timing diagram for JK flip-flop with J=1, K=0 2) Design a T flip-flop using D flip-flop 3) Create state diagram for 3-bit up counter 4) Convert D flip-flop to JK flip-flop 5) What is the output of SR latch when S=1, R=1?<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-6\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 6<\/span>\r\n <h2>Counters & Registers<\/h2>\r\n <p>Up\/Down counters, Ring counters, Shift registers, and Applications<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is a Counter?<\/h3>\r\n <p>A <strong>counter<\/strong> is a sequential circuit that goes through a predetermined sequence of states upon application of clock pulses. Counts number of clock pulses.<\/p>\r\n\r\n <h3>Types of Counters<\/h3>\r\n\r\n <div class=\"feature-grid\">\r\n <div class=\"feature-item\">\u2b06\ufe0f Up Counter: Counts 0\u21921\u21922\u21923...<\/div>\r\n <div class=\"feature-item\">\u2b07\ufe0f Down Counter: Counts 3\u21922\u21921\u21920...<\/div>\r\n <div class=\"feature-item\">\ud83d\udd04 Up\/Down Counter: Both directions<\/div>\r\n <div class=\"feature-item\">\ud83d\udd22 Modulo-N: Counts 0 to N-1<\/div>\r\n <\/div>\r\n\r\n <h3>1. Asynchronous (Ripple) Counter<\/h3>\r\n <p>Flip-flops are NOT clocked simultaneously. Output of one triggers the next.<\/p>\r\n\r\n <p><strong>2-bit Asynchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit:<\/span>\r\nCLK \u2500\u2500\u2510 T-FF \u2510 \u250c T-FF \u2510\r\n \u2502 T=1 \u2502Q\u2080 \u2502 T=1 \u2502Q\u2081\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Timing Diagram:<\/span>\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\u2510 \u250c\u2500\r\n \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518 \u2514\u2500\u2518\r\nQ\u2080 \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\nQ\u2081 \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCount: 00 \u2192 01 \u2192 10 \u2192 11 \u2192 00...\r\n\r\n<span class=\"cm\">MOD-4 Counter (counts 0-3)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-bit Asynchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Counts: 000 \u2192 001 \u2192 010 \u2192 011 \u2192 100 \u2192 101 \u2192 110 \u2192 111 \u2192 000<\/span>\r\n<span class=\"cm\">MOD-8 Counter (8 states)<\/span>\r\n\r\n<span class=\"cm\">Disadvantage: Propagation delay (ripple effect)<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>2. Synchronous Counter<\/h3>\r\n <p>All flip-flops are clocked simultaneously. No ripple delay.<\/p>\r\n\r\n <p><strong>2-bit Synchronous Up Counter:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Circuit using JK Flip-Flops:<\/span>\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\nJ\u2080=1\u2500\u2500\u2502 JK \u2502\u2500\u2500Q\u2080\u2500\u2500\u2502 JK \u2502\u2500\u2500Q\u2081\r\nK\u2080=1\u2500\u2500\u2502 FF0 \u2502 \u2502 FF1 \u2502\r\nCLK\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518 J\u2081\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n K\u2081\r\n\r\nJ\u2081 = K\u2081 = Q\u2080\r\n\r\n<span class=\"cm\">State Table:<\/span>\r\nQ\u2081 Q\u2080 | J\u2081K\u2081 J\u2080K\u2080 | Next\r\n 0 0 | 0X 11 | 01\r\n 0 1 | 1X 11 | 10\r\n 1 0 | X0 11 | 11\r\n 1 1 | X1 11 | 00\r\n<\/pre><\/div>\r\n\r\n <h3>3. Decade Counter (MOD-10)<\/h3>\r\n <p>Counts from 0 to 9, then resets to 0. Uses 4 flip-flops but only 10 states.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">BCD Counter:<\/span>\r\nCount: 0000 \u2192 0001 \u2192 0010 \u2192 ... \u2192 1001 \u2192 0000\r\n\r\n<span class=\"cm\">IC 7490: Decade Counter chip<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>4. Ring Counter<\/h3>\r\n <p>Shift register with output fed back to input. Circulates single '1' bit.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit Ring Counter:<\/span>\r\n\r\nD-FF\u2080 \u2192 D-FF\u2081 \u2192 D-FF\u2082 \u2192 D-FF\u2083 \u2192\u2510\r\n \u2191 \u2502\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Sequence:<\/span>\r\nQ\u2083Q\u2082Q\u2081Q\u2080\r\n1000 \u2192 0100 \u2192 0010 \u2192 0001 \u2192 1000...\r\n\r\n<span class=\"cm\">Applications: State machines, sequence generators<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>5. Johnson Counter (Twisted Ring)<\/h3>\r\n <p>Ring counter with inverted feedback. Has 2N states for N flip-flops.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit Johnson Counter:<\/span>\r\n\r\nD-FF\u2080 \u2192 D-FF\u2081 \u2192 D-FF\u2082 \u2192 D-FF\u2083 \u2192\u2510\r\n \u2191 NOT\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Sequence (8 states):<\/span>\r\n0000 \u2192 1000 \u2192 1100 \u2192 1110 \u2192 1111 \u2192 0111 \u2192 0011 \u2192 0001 \u2192 0000\r\n<\/pre><\/div>\r\n\r\n <h3>Registers<\/h3>\r\n <p>A <strong>register<\/strong> is a group of flip-flops used to store multiple bits of data. Each flip-flop stores one bit.<\/p>\r\n\r\n <h3>1. Parallel-In Parallel-Out (PIPO) Register<\/h3>\r\n <p>All bits loaded and read simultaneously.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit PIPO Register:<\/span>\r\n\r\nD\u2083\u2500\u2500D-FF\u2083\u2500\u2500Q\u2083 D\u2082\u2500\u2500D-FF\u2082\u2500\u2500Q\u2082 D\u2081\u2500\u2500D-FF\u2081\u2500\u2500Q\u2081 D\u2080\u2500\u2500D-FF\u2080\u2500\u2500Q\u2080\r\n \u2502 \u2502 \u2502 \u2502\r\n CLK \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n\r\n<span class=\"cm\">All data loaded at once on clock edge<\/span>\r\n<span class=\"cm\">All data read at once<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>2. Serial-In Serial-Out (SISO) Register<\/h3>\r\n <p>Data shifted in and out one bit at a time. Basic shift register.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">4-bit SISO (Right Shift):<\/span>\r\n\r\nDIN \u2500\u2500 D-FF\u2080 \u2500 D-FF\u2081 \u2500 D-FF\u2082 \u2500 D-FF\u2083 \u2500\u2500 DOUT\r\n \u2502 \u2502 \u2502 \u2502\r\n CLK \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n\r\n<span class=\"cm\">Example: Input 1011 (MSB first)<\/span>\r\nCLK State\r\n 0 0000 (Initial)\r\n 1 1000 (Input 1)\r\n 2 1100 (Input 0)\r\n 3 1110 (Input 1)\r\n 4 1111 (Input 1)\r\n<\/pre><\/div>\r\n\r\n <h3>3. Serial-In Parallel-Out (SIPO) Register<\/h3>\r\n <p>Data shifted in serially, read out in parallel. Serial-to-parallel conversion.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Application: UART receiver, SPI communication<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>4. Parallel-In Serial-Out (PISO) Register<\/h3>\r\n <p>Data loaded in parallel, shifted out serially. Parallel-to-serial conversion.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Application: UART transmitter, data serialization<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Shift Register Modes<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Mode<\/th><th>Description<\/th><th>Application<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Right Shift<\/td><td>Bits shift right, divide by 2<\/td><td>Division, serial output<\/td><\/tr>\r\n <tr><td>Left Shift<\/td><td>Bits shift left, multiply by 2<\/td><td>Multiplication, serial output<\/td><\/tr>\r\n <tr><td>Rotate Right<\/td><td>MSB\u2192LSB (circular)<\/td><td>Rotation, code generation<\/td><\/tr>\r\n <tr><td>Rotate Left<\/td><td>LSB\u2192MSB (circular)<\/td><td>Rotation, code generation<\/td><\/tr>\r\n <tr><td>Bidirectional<\/td><td>Shift both directions<\/td><td>Universal shift register<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Universal Shift Register<\/h3>\r\n <p>Can perform all shift operations: left, right, parallel load, parallel read.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Mode Select (S\u2081S\u2080):<\/span>\r\nS\u2081 S\u2080 | Operation\r\n0 0 | No change (Hold)\r\n0 1 | Shift Right\r\n1 0 | Shift Left\r\n1 1 | Parallel Load\r\n\r\n<span class=\"cm\">IC 74195: 4-bit universal shift register<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Applications of Counters<\/h3>\r\n\r\n <ul>\r\n <li><strong>Frequency Division:<\/strong> MOD-N counter divides frequency by N<\/li>\r\n <li><strong>Digital Clock:<\/strong> MOD-60 for seconds\/minutes, MOD-24 for hours<\/li>\r\n <li><strong>Event Counting:<\/strong> Counting products, pulses, events<\/li>\r\n <li><strong>Timing Circuits:<\/strong> Generating time delays<\/li>\r\n <li><strong>Address Generation:<\/strong> Memory addressing in CPUs<\/li>\r\n <li><strong>Sequence Generation:<\/strong> State machines, control logic<\/li>\r\n <\/ul>\r\n\r\n <h3>Applications of Registers<\/h3>\r\n\r\n <ul>\r\n <li><strong>Data Storage:<\/strong> CPU registers (accumulator, program counter)<\/li>\r\n <li><strong>Data Transfer:<\/strong> Buffer between components<\/li>\r\n <li><strong>Serial Communication:<\/strong> UART, SPI, I2C<\/li>\r\n <li><strong>Arithmetic Operations:<\/strong> Shifting for multiply\/divide<\/li>\r\n <li><strong>Timing & Synchronization:<\/strong> Pipeline registers<\/li>\r\n <li><strong>Data Serialization:<\/strong> Parallel to serial conversion<\/li>\r\n <\/ul>\r\n\r\n <h3>Counter ICs<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Type<\/th><th>Description<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>7490<\/td><td>Decade<\/td><td>MOD-10 asynchronous counter<\/td><\/tr>\r\n <tr><td>7493<\/td><td>Binary<\/td><td>4-bit binary counter (MOD-16)<\/td><\/tr>\r\n <tr><td>74190<\/td><td>Up\/Down<\/td><td>Synchronous BCD up\/down counter<\/td><\/tr>\r\n <tr><td>74191<\/td><td>Up\/Down<\/td><td>Synchronous binary up\/down counter<\/td><\/tr>\r\n <tr><td>74193<\/td><td>Up\/Down<\/td><td>4-bit binary up\/down counter<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Design a MOD-6 counter using JK flip-flops 2) Draw timing diagram for 3-bit ripple counter 3) Design a 4-bit SISO shift register 4) What is the output sequence of a 3-bit Johnson counter? 5) Calculate frequency at output of MOD-8 counter if input is 1 MHz<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-7\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 7<\/span>\r\n <h2>Memory Systems<\/h2>\r\n <p>RAM, ROM, SRAM, DRAM, Memory organization, and Address decoding<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>What is Memory?<\/h3>\r\n <p><strong>Memory<\/strong> is a digital circuit that stores data in binary form. Essential component of all computer systems.<\/p>\r\n\r\n <h3>Memory Classification<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Memory Hierarchy:<\/span>\r\n\r\n Memory\r\n \u2502\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502\r\n Volatile Non-Volatile\r\n (RAM) (ROM)\r\n \u2502 \u2502\r\n \u250c\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2534\u2500\u2500\u2500\u2500\u2510\r\n \u2502 \u2502 \u2502 \u2502\r\n SRAM DRAM ROM EPROM\r\n EEPROM\r\n Flash\r\n<\/pre><\/div>\r\n\r\n <h3>1. RAM (Random Access Memory)<\/h3>\r\n <p><strong>Volatile memory:<\/strong> Data lost when power off. Read and Write operations.<\/p>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n\r\n <p><strong>A) SRAM (Static RAM)<\/strong><\/p>\r\n <ul>\r\n <li>Uses flip-flops (6 transistors per bit)<\/li>\r\n <li>Faster than DRAM<\/li>\r\n <li>No refresh required<\/li>\r\n <li>More expensive<\/li>\r\n <li>Lower density<\/li>\r\n <li>Used in: Cache memory, CPU registers<\/li>\r\n <\/ul>\r\n\r\n <p><strong>B) DRAM (Dynamic RAM)<\/strong><\/p>\r\n <ul>\r\n <li>Uses capacitors (1 transistor + 1 capacitor per bit)<\/li>\r\n <li>Slower than SRAM<\/li>\r\n <li>Requires periodic refresh (capacitor leaks)<\/li>\r\n <li>Cheaper<\/li>\r\n <li>Higher density<\/li>\r\n <li>Used in: Main memory (system RAM)<\/li>\r\n <\/ul>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>SRAM<\/th><th>DRAM<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Speed<\/td><td>Fast (2-10 ns)<\/td><td>Slower (50-70 ns)<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Expensive<\/td><td>Cheap<\/td><\/tr>\r\n <tr><td>Density<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Refresh<\/td><td>Not needed<\/td><td>Needed<\/td><\/tr>\r\n <tr><td>Complexity<\/td><td>Complex (6T)<\/td><td>Simple (1T1C)<\/td><\/tr>\r\n <tr><td>Usage<\/td><td>Cache<\/td><td>Main memory<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>2. ROM (Read-Only Memory)<\/h3>\r\n <p><strong>Non-volatile memory:<\/strong> Data retained when power off. Primarily read operations.<\/p>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n\r\n <p><strong>A) Mask ROM<\/strong><\/p>\r\n <ul>\r\n <li>Programmed during manufacturing<\/li>\r\n <li>Cannot be modified<\/li>\r\n <li>Used in: BIOS, firmware, embedded systems<\/li>\r\n <\/ul>\r\n\r\n <p><strong>B) PROM (Programmable ROM)<\/strong><\/p>\r\n <ul>\r\n <li>One-time programmable by user<\/li>\r\n <li>Uses fuses that can be blown<\/li>\r\n <li>Cannot be erased once programmed<\/li>\r\n <\/ul>\r\n\r\n <p><strong>C) EPROM (Erasable PROM)<\/strong><\/p>\r\n <ul>\r\n <li>Can be erased using UV light<\/li>\r\n <li>Reprogrammable<\/li>\r\n <li>Has transparent window on top<\/li>\r\n <li>Erase time: 15-20 minutes<\/li>\r\n <\/ul>\r\n\r\n <p><strong>D) EEPROM (Electrically Erasable PROM)<\/strong><\/p>\r\n <ul>\r\n <li>Can be erased electrically (byte-by-byte)<\/li>\r\n <li>No UV light needed<\/li>\r\n <li>Slower write, faster read<\/li>\r\n <li>Used in: Configuration data, calibration<\/li>\r\n <\/ul>\r\n\r\n <p><strong>E) Flash Memory<\/strong><\/p>\r\n <ul>\r\n <li>Type of EEPROM, erases in blocks<\/li>\r\n <li>Fast, high density<\/li>\r\n <li>Used in: USB drives, SSDs, memory cards<\/li>\r\n <\/ul>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Type<\/th><th>Erase Method<\/th><th>Write Speed<\/th><th>Application<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Mask ROM<\/td><td>Cannot erase<\/td><td>N\/A<\/td><td>BIOS, firmware<\/td><\/tr>\r\n <tr><td>PROM<\/td><td>Cannot erase<\/td><td>Fast<\/td><td>One-time programming<\/td><\/tr>\r\n <tr><td>EPROM<\/td><td>UV light<\/td><td>Slow<\/td><td>Development, testing<\/td><\/tr>\r\n <tr><td>EEPROM<\/td><td>Electrical (byte)<\/td><td>Very slow<\/td><td>Config, calibration<\/td><\/tr>\r\n <tr><td>Flash<\/td><td>Electrical (block)<\/td><td>Medium<\/td><td>Storage, USB, SSD<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Memory Organization<\/h3>\r\n\r\n <p><strong>Memory Specifications:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Capacity:<\/strong> Total number of bits (M \u00d7 N)<\/li>\r\n <li><strong>M:<\/strong> Number of words (addressable locations)<\/li>\r\n <li><strong>N:<\/strong> Number of bits per word (word size)<\/li>\r\n <li><strong>Address lines:<\/strong> log\u2082(M) lines needed<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: 1K \u00d7 8 Memory<\/span>\r\n\r\n1K = 1024 words\r\n8 = 8 bits per word\r\n\r\nTotal capacity: 1024 \u00d7 8 = 8192 bits = 8 Kb = 1 KB\r\n\r\nAddress lines needed: log\u2082(1024) = 10 lines\r\nData lines: 8 lines\r\n\r\n<span class=\"cm\">Memory Block Diagram:<\/span>\r\n\r\nA\u2080-A\u2089 (10 lines) \u2500\u2500\u2500\u2500\u2510\r\n \u2502 1K\u00d78\r\nCS (Chip Select) \u2500\u2500\u2500\u2500\u2500\u2524 Memory \u2500\u2500\u2500\u2500 D\u2080-D\u2087 (8 lines)\r\nR\/W\u0304 (Read\/Write) \u2500\u2500\u2500\u2500\u2500\u2524\r\n \u2514\r\n\r\n<span class=\"cm\">Address Range: 0x000 to 0x3FF (0 to 1023)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Common Memory Sizes:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Specification<\/th><th>Words<\/th><th>Address Bits<\/th><th>Total Capacity<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>256 \u00d7 4<\/td><td>256<\/td><td>8<\/td><td>1 Kb<\/td><\/tr>\r\n <tr><td>1K \u00d7 8<\/td><td>1024<\/td><td>10<\/td><td>8 Kb = 1 KB<\/td><\/tr>\r\n <tr><td>4K \u00d7 8<\/td><td>4096<\/td><td>12<\/td><td>32 Kb = 4 KB<\/td><\/tr>\r\n <tr><td>64K \u00d7 8<\/td><td>65,536<\/td><td>16<\/td><td>512 Kb = 64 KB<\/td><\/tr>\r\n <tr><td>1M \u00d7 8<\/td><td>1,048,576<\/td><td>20<\/td><td>8 Mb = 1 MB<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Memory Expansion<\/h3>\r\n\r\n <p><strong>1. Word Expansion (Increasing Word Size)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Create 1K\u00d716 using two 1K\u00d78 chips<\/span>\r\n\r\nA\u2080-A\u2089 \u2500\u2500\u252c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2500\u2500 D\u2080-D\u2087\r\n \u2502 Chip 1\r\nCS \u2500\u2500\u2500\u2500\u253c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2500\u2500 D\u2088-D\u2081\u2085\r\n \u2502 Chip 2\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2518\r\n\r\n<span class=\"cm\">Same addresses, more data bits<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. Word Count Expansion (Increasing Number of Words)<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: Create 2K\u00d78 using two 1K\u00d78 chips<\/span>\r\n\r\nA\u2080-A\u2089 \u2500\u2500\u252c\u2500\u2500\u2500 1K\u00d78 \u2500\u2500\u2510\r\n \u2502 Chip 1 \u251c\u2500\u2500\u2500 D\u2080-D\u2087\r\nA\u2081\u2080 \u2500\u2500\u2500\u2500\u2524 \u2502\r\nDecoder \u2502 1K\u00d78 \u2500\u2500\u2500\u2518\r\n \u2514\u2500\u2500\u2500 Chip 2\r\n\r\n<span class=\"cm\">A\u2081\u2080=0: Chip 1 (0x000-0x3FF)<\/span>\r\n<span class=\"cm\">A\u2081\u2080=1: Chip 2 (0x400-0x7FF)<\/span>\r\n<\/pre><\/div>\r\n\r\n <h3>Address Decoding<\/h3>\r\n <p>Process of selecting specific memory chip based on address.<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Linear Decoding (Simple but wasteful):<\/span>\r\n\r\nA\u2081\u2080 \u2500\u2500NOT\u2500\u2500 CS\u0304\u2081 (Chip 1: A\u2081\u2080=0)\r\nA\u2081\u2080 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 CS\u0304\u2082 (Chip 2: A\u2081\u2080=1)\r\n\r\n<span class=\"cm\">Full Decoding (Using Decoder):<\/span>\r\n\r\nA\u2081\u2080-A\u2081\u2081 \u2500\u2500\u2500\u2510\r\n 2:4 CS\u0304\u2080 \u2192 Chip 0\r\n Decoder CS\u0304\u2081 \u2192 Chip 1\r\n CS\u0304\u2082 \u2192 Chip 2\r\n CS\u0304\u2083 \u2192 Chip 3\r\n<\/pre><\/div>\r\n\r\n <h3>Memory Timing<\/h3>\r\n\r\n <p><strong>Read Cycle Timing:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Memory Read Timing Diagram:<\/span>\r\n\r\nAddress \u2500\u2500\u2510 Valid Address \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCS\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 (High for Read)\r\n\r\nData \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 Valid Data \u250c\u2500\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190\u2500 tACC \u2500\u2192 (Access Time)\r\n\r\n<span class=\"cm\">tACC: Time from address valid to data valid<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>Write Cycle Timing:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\nAddress \u2500\u2500\u2510 Valid Address \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nCS\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nR\/W\u0304 \u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500 (Low for Write)\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\nData \u2500\u2500\u2500\u2500\u2500\u2510 Valid Data \u250c\u2500\u2500\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190\u2500 tWR \u2500\u2192 (Write Time)\r\n<\/pre><\/div>\r\n\r\n <h3>Memory ICs<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>IC Number<\/th><th>Type<\/th><th>Capacity<\/th><th>Organization<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>2114<\/td><td>SRAM<\/td><td>4 Kb<\/td><td>1K \u00d7 4<\/td><\/tr>\r\n <tr><td>6116<\/td><td>SRAM<\/td><td>16 Kb<\/td><td>2K \u00d7 8<\/td><\/tr>\r\n <tr><td>6264<\/td><td>SRAM<\/td><td>64 Kb<\/td><td>8K \u00d7 8<\/td><\/tr>\r\n <tr><td>2732<\/td><td>EPROM<\/td><td>32 Kb<\/td><td>4K \u00d7 8<\/td><\/tr>\r\n <tr><td>2764<\/td><td>EPROM<\/td><td>64 Kb<\/td><td>8K \u00d7 8<\/td><\/tr>\r\n <tr><td>27C256<\/td><td>EPROM<\/td><td>256 Kb<\/td><td>32K \u00d7 8<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Calculate address lines needed for 16K \u00d7 8 memory 2) Design memory system with 4K \u00d7 8 using two 2K \u00d7 8 chips 3) Compare SRAM vs DRAM 4) What is address range for 1K \u00d7 8 memory starting at 0x2000? 5) Draw timing diagram for memory read cycle<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"unit\" id=\"unit-8\">\r\n <div class=\"unit-header\">\r\n <span class=\"unit-num-badge\">Unit 8<\/span>\r\n <h2>Advanced Topics<\/h2>\r\n <p>PLDs, FPGAs, Karnaugh Maps, Quine-McCluskey method, and Modern Digital Design<\/p>\r\n <\/div>\r\n <div class=\"unit-body\">\r\n <h3>Karnaugh Maps (K-Maps)<\/h3>\r\n <p><strong>Karnaugh Map<\/strong> is a graphical method for simplifying Boolean expressions. Alternative to Boolean algebra.<\/p>\r\n\r\n <p><strong>2-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> B\r\nA 0 1\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n0 \u2502 0 1\r\n1 \u2502 2 3\r\n\r\n<span class=\"cm\">Example: F(A,B) = \u03a3m(1,2,3)<\/span>\r\n\r\n B\r\nA 0 1\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n0 \u2502 0 1\r\n1 \u2502 1 1\r\n\r\n<span class=\"cm\">Grouping:<\/span>\r\nGroup 1 (1,3): B\r\nGroup 2 (2,3): A\r\n\r\nF = A + B\r\n<\/pre><\/div>\r\n\r\n <p><strong>3-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 3 2\r\n 1 \u2502 4 5 7 6\r\n\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,7)<\/span>\r\n\r\n BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 1 0\r\n 1 \u2502 0 1 1 0\r\n\r\n<span class=\"cm\">Grouping: Vertical column (1,3,5,7)<\/span>\r\nF = C\r\n\r\n<span class=\"cm\">Gray code ordering! (00,01,11,10)<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>4-Variable K-Map:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\"> CD\r\nAB 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 00 \u2502 0 1 3 2\r\n 01 \u2502 4 5 7 6\r\n 11 \u2502 12 13 15 14\r\n 10 \u2502 8 9 11 10\r\n\r\n<span class=\"cm\">Rules for Grouping:<\/span>\r\n1. Group size: 1, 2, 4, 8, 16 (powers of 2)\r\n2. Groups should be rectangular\r\n3. Make largest possible groups\r\n4. Groups can overlap\r\n5. Groups can wrap around edges\r\n6. Minimize number of groups\r\n<\/pre><\/div>\r\n\r\n <p><strong>Example: Simplify using K-Map<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">F(A,B,C,D) = \u03a3m(0,2,5,7,8,10,13,15)<\/span>\r\n\r\n CD\r\nAB 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 00 \u2502 1 0 0 1 Group 1: m(0,2,8,10) = B'D'\r\n 01 \u2502 0 1 1 0 Group 2: m(5,7,13,15) = BD\r\n 11 \u2502 0 1 1 0\r\n 10 \u2502 1 0 0 1\r\n\r\nF = B'D' + BD = B \u2295 D\r\n<\/pre><\/div>\r\n\r\n <p><strong>Don't Care Conditions (X):<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">F(A,B,C) = \u03a3m(1,3,7) + d(5,6)<\/span>\r\n<span class=\"cm\">d = don't care (can be 0 or 1)<\/span>\r\n\r\nUse X strategically to make larger groups!\r\n\r\n BC\r\nA 00 01 11 10\r\n \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n 0 \u2502 0 1 1 0\r\n 1 \u2502 0 X 1 X\r\n\r\n<span class=\"cm\">Include d(5) in group with m(1,7)<\/span>\r\nF = C\r\n<\/pre><\/div>\r\n\r\n <h3>Quine-McCluskey Method<\/h3>\r\n <p>Tabular method for simplification. Better for >4 variables and computer implementation.<\/p>\r\n\r\n <p><strong>Steps:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Step 1:<\/strong> List minterms in binary grouped by number of 1s<\/li>\r\n <li><strong>Step 2:<\/strong> Compare adjacent groups, combine terms differing by 1 bit<\/li>\r\n <li><strong>Step 3:<\/strong> Replace differing bit with dash (-)<\/li>\r\n <li><strong>Step 4:<\/strong> Repeat until no more combinations possible<\/li>\r\n <li><strong>Step 5:<\/strong> Create prime implicant table<\/li>\r\n <li><strong>Step 6:<\/strong> Select minimum set of prime implicants<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Example: F(A,B,C) = \u03a3m(1,3,5,6,7)<\/span>\r\n\r\n<span class=\"cm\">Step 1: List by number of 1s<\/span>\r\nGroup 0: m\u2081 = 001\r\nGroup 1: m\u2083 = 011\r\n m\u2085 = 101\r\nGroup 2: m\u2086 = 110\r\n m\u2087 = 111\r\n\r\n<span class=\"cm\">Step 2: Combine (differ by 1 bit)<\/span>\r\nm\u2081,m\u2083: 0-1 (BC)\r\nm\u2081,m\u2085: -01 (A'C)\r\nm\u2083,m\u2087: -11 (BC)\r\nm\u2085,m\u2087: 1-1 (AC)\r\nm\u2086,m\u2087: 11- (AB)\r\n\r\n<span class=\"cm\">Step 3: Prime Implicants<\/span>\r\nBC, A'C, AC, AB\r\n\r\n<span class=\"cm\">Step 4: Minimum cover<\/span>\r\nF = A'C + AB + BC\r\n<\/pre><\/div>\r\n\r\n <h3>Programmable Logic Devices (PLDs)<\/h3>\r\n <p>ICs that can be programmed to implement custom logic functions. User-configurable hardware.<\/p>\r\n\r\n <h3>Types of PLDs<\/h3>\r\n\r\n <p><strong>1. PROM (Programmable ROM)<\/strong><\/p>\r\n <ul>\r\n <li>Fixed AND array, programmable OR array<\/li>\r\n <li>Simple, but limited flexibility<\/li>\r\n <\/ul>\r\n\r\n <p><strong>2. PAL (Programmable Array Logic)<\/strong><\/p>\r\n <ul>\r\n <li>Programmable AND array, fixed OR array<\/li>\r\n <li>Fast, low cost<\/li>\r\n <li>Cannot share product terms between outputs<\/li>\r\n <\/ul>\r\n\r\n <p><strong>3. PLA (Programmable Logic Array)<\/strong><\/p>\r\n <ul>\r\n <li>Both AND and OR arrays programmable<\/li>\r\n <li>More flexible than PAL<\/li>\r\n <li>Can share product terms<\/li>\r\n <li>Slower than PAL<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">PLD Structure:<\/span>\r\n\r\nInputs \u2192 AND Array \u2192 OR Array \u2192 Outputs\r\n\r\n<span class=\"cm\">PAL: Programmable AND, Fixed OR<\/span>\r\n<span class=\"cm\">PLA: Programmable AND, Programmable OR<\/span>\r\n<span class=\"cm\">PROM: Fixed AND, Programmable OR<\/span>\r\n<\/pre><\/div>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>PAL<\/th><th>PLA<\/th><th>PROM<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>AND Array<\/td><td>Programmable<\/td><td>Programmable<\/td><td>Fixed<\/td><\/tr>\r\n <tr><td>OR Array<\/td><td>Fixed<\/td><td>Programmable<\/td><td>Programmable<\/td><\/tr>\r\n <tr><td>Speed<\/td><td>Fast<\/td><td>Medium<\/td><td>Fast<\/td><\/tr>\r\n <tr><td>Flexibility<\/td><td>Medium<\/td><td>High<\/td><td>Low<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Low<\/td><td>Medium<\/td><td>Low<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Complex PLDs (CPLDs)<\/h3>\r\n <p>Multiple PAL\/PLA blocks connected via programmable interconnects.<\/p>\r\n\r\n <ul>\r\n <li>More logic capacity than simple PLDs<\/li>\r\n <li>Non-volatile (retains configuration when powered off)<\/li>\r\n <li>Predictable timing<\/li>\r\n <li>Examples: Xilinx CoolRunner, Altera MAX<\/li>\r\n <li>Applications: Glue logic, state machines, interface logic<\/li>\r\n <\/ul>\r\n\r\n <h3>Field-Programmable Gate Arrays (FPGAs)<\/h3>\r\n <p>Most advanced and flexible PLDs. Array of configurable logic blocks (CLBs).<\/p>\r\n\r\n <p><strong>FPGA Structure:<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502<\/span>\r\n<span class=\"cm\">\u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502 \u2190 Configurable Logic Blocks<\/span>\r\n<span class=\"cm\">\u2502 \u2502 \u2502 \u2502 \u2502 \u2502 \u2502<\/span>\r\n<span class=\"cm\">\u2502 CLB CLB CLB CLB CLB \u2502<\/span>\r\n<span class=\"cm\">\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/span>\r\n Programmable Interconnects\r\n\r\n<span class=\"cm\">Each CLB contains:<\/span>\r\n- Look-Up Tables (LUTs) for logic\r\n- Flip-flops for storage\r\n- Multiplexers for routing\r\n<\/pre><\/div>\r\n\r\n <p><strong>FPGA Features:<\/strong><\/p>\r\n <ul>\r\n <li>Very high logic capacity (millions of gates)<\/li>\r\n <li>Reconfigurable (can be reprogrammed)<\/li>\r\n <li>Contains RAM blocks, DSP blocks, I\/O blocks<\/li>\r\n <li>Volatile configuration (needs external memory)<\/li>\r\n <li>Complex, requires specialized tools<\/li>\r\n <\/ul>\r\n\r\n <p><strong>FPGA vs CPLD:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>CPLD<\/th><th>FPGA<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Capacity<\/td><td>10K gates<\/td><td>1M+ gates<\/td><\/tr>\r\n <tr><td>Architecture<\/td><td>PAL-based<\/td><td>LUT-based<\/td><\/tr>\r\n <tr><td>Configuration<\/td><td>Non-volatile<\/td><td>Volatile (SRAM)<\/td><\/tr>\r\n <tr><td>Timing<\/td><td>Predictable<\/td><td>Unpredictable<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Cost<\/td><td>Low<\/td><td>High<\/td><\/tr>\r\n <tr><td>Use<\/td><td>Simple logic<\/td><td>Complex systems<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>FPGA Applications<\/h3>\r\n\r\n <ul>\r\n <li><strong>Prototyping:<\/strong> ASIC design verification<\/li>\r\n <li><strong>DSP:<\/strong> Signal processing, image processing<\/li>\r\n <li><strong>Communication:<\/strong> Modems, routers, base stations<\/li>\r\n <li><strong>Aerospace:<\/strong> Satellites, avionics (radiation-tolerant)<\/li>\r\n <li><strong>Industrial:<\/strong> Motor control, robotics<\/li>\r\n <li><strong>AI\/ML:<\/strong> Neural network acceleration<\/li>\r\n <li><strong>Automotive:<\/strong> ADAS, autonomous driving<\/li>\r\n <li><strong>Medical:<\/strong> Medical imaging, diagnostics<\/li>\r\n <\/ul>\r\n\r\n <h3>FPGA Vendors<\/h3>\r\n\r\n <table class=\"data-table\">\r\n <thead><tr><th>Vendor<\/th><th>FPGA Family<\/th><th>Features<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Xilinx (AMD)<\/td><td>Spartan, Artix, Kintex, Virtex<\/td><td>Market leader, high performance<\/td><\/tr>\r\n <tr><td>Intel (Altera)<\/td><td>Cyclone, Arria, Stratix<\/td><td>Good tools, wide adoption<\/td><\/tr>\r\n <tr><td>Lattice<\/td><td>iCE40, ECP5, CrossLink<\/td><td>Low power, small size<\/td><\/tr>\r\n <tr><td>Microchip<\/td><td>PolarFire, IGLOO<\/td><td>Low power, secure<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Hardware Description Languages (HDLs)<\/h3>\r\n <p>Used to design and program FPGAs\/CPLDs.<\/p>\r\n\r\n <p><strong>1. Verilog<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">\/\/ 2-to-1 Multiplexer in Verilog<\/span>\r\n<span class=\"kw\">module<\/span> mux2to1 (\r\n <span class=\"kw\">input<\/span> a, b, sel,\r\n <span class=\"kw\">output<\/span> y\r\n);\r\n <span class=\"kw\">assign<\/span> y = sel ? b : a;\r\n<span class=\"kw\">endmodule<\/span>\r\n<\/pre><\/div>\r\n\r\n <p><strong>2. VHDL<\/strong><\/p>\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">-- 2-to-1 Multiplexer in VHDL<\/span>\r\n<span class=\"kw\">entity<\/span> mux2to1 <span class=\"kw\">is<\/span>\r\n <span class=\"kw\">port<\/span> (a, b, sel : <span class=\"kw\">in<\/span> std_logic;\r\n y : <span class=\"kw\">out<\/span> std_logic);\r\n<span class=\"kw\">end<\/span> mux2to1;\r\n\r\n<span class=\"kw\">architecture<\/span> behav <span class=\"kw\">of<\/span> mux2to1 <span class=\"kw\">is<\/span>\r\n<span class=\"kw\">begin<\/span>\r\n y <= b <span class=\"kw\">when<\/span> sel = '1' <span class=\"kw\">else<\/span> a;\r\n<span class=\"kw\">end<\/span> behav;\r\n<\/pre><\/div>\r\n\r\n <h3>ASIC (Application-Specific Integrated Circuit)<\/h3>\r\n <p>Custom-designed ICs for specific applications. Not programmable like FPGAs.<\/p>\r\n\r\n <p><strong>ASIC vs FPGA:<\/strong><\/p>\r\n <table class=\"data-table\">\r\n <thead><tr><th>Feature<\/th><th>ASIC<\/th><th>FPGA<\/th><\/tr><\/thead>\r\n <tbody>\r\n <tr><td>Flexibility<\/td><td>Fixed (cannot change)<\/td><td>Reconfigurable<\/td><\/tr>\r\n <tr><td>Development Cost<\/td><td>Very high (millions)<\/td><td>Low<\/td><\/tr>\r\n <tr><td>Unit Cost<\/td><td>Low (in volume)<\/td><td>High<\/td><\/tr>\r\n <tr><td>Performance<\/td><td>Highest<\/td><td>Lower<\/td><\/tr>\r\n <tr><td>Power<\/td><td>Lowest<\/td><td>Higher<\/td><\/tr>\r\n <tr><td>Time-to-Market<\/td><td>Long (months)<\/td><td>Short (days)<\/td><\/tr>\r\n <tr><td>Use Case<\/td><td>High volume products<\/td><td>Low volume, prototyping<\/td><\/tr>\r\n <\/tbody>\r\n <\/table>\r\n\r\n <h3>Modern Digital Design Flow<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">1. Specification<\/span>\r\n Define requirements, features, constraints\r\n \u2193\r\n<span class=\"cm\">2. Architecture Design<\/span>\r\n Block diagrams, high-level design\r\n \u2193\r\n<span class=\"cm\">3. RTL Design (HDL Coding)<\/span>\r\n Write Verilog\/VHDL code\r\n \u2193\r\n<span class=\"cm\">4. Simulation & Verification<\/span>\r\n Testbenches, functional verification\r\n \u2193\r\n<span class=\"cm\">5. Synthesis<\/span>\r\n Convert HDL to gate-level netlist\r\n \u2193\r\n<span class=\"cm\">6. Place & Route<\/span>\r\n Map logic to physical layout\r\n \u2193\r\n<span class=\"cm\">7. Timing Analysis<\/span>\r\n Check timing constraints, optimize\r\n \u2193\r\n<span class=\"cm\">8. Bitstream Generation<\/span>\r\n Create configuration file for FPGA\r\n \u2193\r\n<span class=\"cm\">9. Programming & Testing<\/span>\r\n Load onto hardware, test in real environment\r\n<\/pre><\/div>\r\n\r\n <h3>Timing Concepts<\/h3>\r\n\r\n <p><strong>Setup Time (tsu):<\/strong> Minimum time data must be stable BEFORE clock edge<\/p>\r\n <p><strong>Hold Time (th):<\/strong> Minimum time data must be stable AFTER clock edge<\/p>\r\n <p><strong>Clock-to-Q Delay (tCQ):<\/strong> Time from clock edge to output change<\/p>\r\n <p><strong>Propagation Delay (tp):<\/strong> Time for signal to pass through gate<\/p>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Timing Diagram:<\/span>\r\n\r\nCLK \u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\r\n \u2514\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2518\r\n\r\nDATA \u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\r\n \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518\r\n\r\n \u2190tsu\u2192 \u2190th\u2192\r\n \u2191 CLK edge\r\n\r\n<span class=\"cm\">Violation:<\/span>\r\n- Setup Violation: Data changes too close to clock edge\r\n- Hold Violation: Data changes too soon after clock edge\r\n<\/pre><\/div>\r\n\r\n <h3>Clock Frequency & Period<\/h3>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Maximum Clock Frequency:<\/span>\r\n\r\nfmax = 1 \/ (tCQ + tlogic + tsu)\r\n\r\nWhere:\r\ntCQ = Clock-to-Q delay of source FF\r\ntlogic = Combinational logic delay\r\ntsu = Setup time of destination FF\r\n\r\n<span class=\"cm\">Example:<\/span>\r\ntCQ = 2 ns, tlogic = 8 ns, tsu = 1 ns\r\nfmax = 1 \/ (2+8+1) ns = 1\/11 ns = 90.9 MHz\r\n<\/pre><\/div>\r\n\r\n <h3>Metastability<\/h3>\r\n <p>When a flip-flop violates setup\/hold time, output may become unstable (neither 0 nor 1).<\/p>\r\n\r\n <ul>\r\n <li><strong>Cause:<\/strong> Asynchronous inputs violating timing<\/li>\r\n <li><strong>Solution:<\/strong> Use synchronizers (2-FF chain)<\/li>\r\n <li><strong>Impact:<\/strong> Unpredictable behavior, system failure<\/li>\r\n <\/ul>\r\n\r\n <h3>Power Consumption in Digital Circuits<\/h3>\r\n\r\n <p><strong>Types:<\/strong><\/p>\r\n <ul>\r\n <li><strong>Dynamic Power:<\/strong> Power when switching (CV\u00b2f)<\/li>\r\n <li><strong>Static Power:<\/strong> Leakage power when idle<\/li>\r\n <li><strong>Short-Circuit Power:<\/strong> During transition<\/li>\r\n <\/ul>\r\n\r\n <div class=\"code-block\"><pre>\r\n<span class=\"cm\">Dynamic Power:<\/span>\r\nP = C \u00d7 V\u00b2 \u00d7 f \u00d7 \u03b1\r\n\r\nC = Load capacitance\r\nV = Supply voltage\r\nf = Clock frequency\r\n\u03b1 = Switching activity factor (0 to 1)\r\n\r\n<span class=\"cm\">Reducing Power:<\/span>\r\n- Lower voltage\r\n- Reduce clock frequency\r\n- Clock gating (disable unused blocks)\r\n- Power gating (turn off unused blocks)\r\n<\/pre><\/div>\r\n\r\n <h3>Future of Digital Logic Design<\/h3>\r\n\r\n <ul>\r\n <li><strong>3D ICs:<\/strong> Stacking multiple die layers<\/li>\r\n <li><strong>Quantum Computing:<\/strong> Qubits instead of bits<\/li>\r\n <li><strong>Neuromorphic Computing:<\/strong> Brain-inspired architectures<\/li>\r\n <li><strong>Optical Computing:<\/strong> Light-based logic<\/li>\r\n <li><strong>DNA Computing:<\/strong> Biological computation<\/li>\r\n <li><strong>Spintronics:<\/strong> Using electron spin<\/li>\r\n <\/ul>\r\n\r\n <div class=\"practice\">\u270f\ufe0f <strong>Practice:<\/strong> 1) Simplify F(A,B,C,D) = \u03a3m(0,1,2,5,8,9,10) using K-map 2) Compare PAL, PLA, and PROM 3) List advantages of FPGAs over ASICs 4) Calculate maximum clock frequency if tCQ=3ns, tlogic=10ns, tsu=2ns 5) Draw a 3-variable K-map and group minterms<\/div>\r\n <\/div>\r\n <\/div>\r\n\r\n \r\n <div class=\"congrats\">\r\n <h2>\ud83c\udf89 Congratulations!<\/h2>\r\n <p>You've completed Digital Logic Design course! You now have solid foundation in DLD - from number systems to advanced FPGAs and modern digital design. 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