Digital Logic Design
Complete Course

Circuit:
S ──NOR──┬──── Q
    ┌────┘
    │
    └────┐
R ──NOR──┴──── Q'

Truth Table:
S  R  |  Q   Q'  |  State
0  0  |  Q   Q'  |  Hold (No change)
0  1  |  0   1   |  Reset
1  0  |  1   0   |  Set
1  1  |  0   0   |  Invalid (Not allowed!)

Characteristic Equation:
Q(next) = S + R'·Q

Truth Table (Active LOW inputs):
S̄  R̄  |  Q   Q'  |  State
0  0  |  1   1   |  Invalid
0  1  |  1   0   |  Set
1  0  |  0   1   |  Reset
1  1  |  Q   Q'  |  Hold

Block Diagram:
S ──┐
    Enable──── SR Latch ──── Q
R ──┘                   └──── Q'
EN

Truth Table:
EN  S  R  |  Q(next)
0   X  X  |  Q (Hold)
1   0  0  |  Q (Hold)
1   0  1  |  0 (Reset)
1   1  0  |  1 (Set)
1   1  1  |  Invalid

Circuit:
D ──┬───────── S
    │         SR Latch ──── Q
    └──NOT──  R

Truth Table:
EN  D  |  Q(next)
0   X  |  Q (Hold)
1   0  |  0
1   1  |  1

When EN=1: Q follows D
When EN=0: Q holds previous value

Symbol:
S ─────┐
       │  SR
CLK ───┤  FF  ──── Q
       │      └──── Q'
R ─────┘

Truth Table (Positive Edge Triggered):
S  R  |  Q(t+1)  |  Comment
0  0  |   Q(t)   |  No change
0  1  |    0     |  Reset
1  0  |    1     |  Set
1  1  |  Invalid |  Not allowed

Characteristic Equation:
Q(t+1) = S + R'·Q(t)

Symbol:
J ─────┐
       │  JK
CLK ───┤  FF  ──── Q
       │      └──── Q'
K ─────┘

Truth Table:
J  K  |  Q(t+1)  |  Comment
0  0  |   Q(t)   |  No change (Hold)
0  1  |    0     |  Reset
1  0  |    1     |  Set
1  1  |   Q'(t)  |  Toggle

Characteristic Equation:
Q(t+1) = J·Q'(t) + K'·Q(t)

CLK  ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
       └─┘ └─┘ └─┘ └─┘
J    ────────┐     ┌────
K    ──┐     └─────┘
       └────────────────
Q    ──┐   ┌───┐   ┌───
       └───┘   └───┘

J=0,K=1 → Reset (Q=0)
J=1,K=0 → Set (Q=1)
J=1,K=1 → Toggle
J=0,K=0 → Hold

Symbol:
D ─────┐
       │  D
CLK ───┤  FF  ──── Q
       │      └──── Q'
       └

Truth Table:
D  |  Q(t+1)
0  |    0
1  |    1

Characteristic Equation:
Q(t+1) = D

Note: No invalid state, simplest to use

Symbol:
T ─────┐
       │  T
CLK ───┤  FF  ──── Q
       │      └──── Q'
       └

Truth Table:
T  |  Q(t+1)  |  Comment
0  |   Q(t)   |  No change
1  |  Q'(t)   |  Toggle

Characteristic Equation:
Q(t+1) = T·Q'(t) + T'·Q(t) = T ⊕ Q(t)

Excitation Table Comparison:

Q(t)  Q(t+1) |  S  R  |  J  K
  0     0    |  0  X  |  0  X
  0     1    |  1  0  |  1  X
  1     0    |  0  1  |  X  1
  1     1    |  X  0  |  X  0

Conversion Logic:
S = J·Q'
R = K·Q

Block Diagram:
J ──┐         ┌──┐         ┌── Q
    Master FF │  │ Slave FF │
K ──┘    Q────┘  └─── Q ───┘── Q'
CLK ──┬──────────NOT────┐
      │                 │
      └─────────────────┘

Operation:
1. When CLK=1: Master enabled, Slave disabled
   Master captures J, K inputs
2. When CLK=0: Master disabled, Slave enabled
   Slave copies Master output

Advantage: Prevents race conditions

Flip-Flop with Preset (PRE) and Clear (CLR):

PRE ────┐
        │  FF
D   ────┤     ──── Q
CLK ────┤     └──── Q'
        │
CLR ────┘

Truth Table:
PRE  CLR |  Q   Q'  |  Comment
 0    0  |  1   1   |  Invalid
 0    1  |  1   0   |  Preset (Set Q=1)
 1    0  |  0   1   |  Clear (Set Q=0)
 1    1  |  Operates normally with CLK/D

Example: 2-bit Binary Counter

         ┌─────┐
      ┌──│  00 │──┐
      │  └─────┘  │
      │     ↓     │
      │  ┌─────┐  │
      └──│  01 │←─┘
         └─────┘
            ↓
         ┌─────┐
      ┌──│  10 │←─┐
      │  └─────┘  │
      │     ↓     │
      │  ┌─────┐  │
      └──│  11 │──┘
         └─────┘
            ↓
         (back to 00)

States: 00 → 01 → 10 → 11 → 00...

Example: JK Flip-Flop State Table

Present  Inputs |  Next
State    J   K  |  State
  0      0   0  |   0
  0      0   1  |   0
  0      1   0  |   1
  0      1   1  |   1
  1      0   0  |   1
  1      0   1  |   0
  1      1   0  |   1
  1      1   1  |   0

Circuit:
CLK ──┐ T-FF ┐   ┌ T-FF ┐
      │  T=1 │Q₀ │  T=1 │Q₁
      └──────┘   └──────┘

Timing Diagram:
CLK  ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─
       └─┘ └─┘ └─┘ └─┘
Q₀   ──┐   ┌───┐   ┌───
       └───┘   └───┘
Q₁   ──┐       ┌───────
       └───────┘

Count: 00 → 01 → 10 → 11 → 00...

MOD-4 Counter (counts 0-3)

Counts: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000
MOD-8 Counter (8 states)

Disadvantage: Propagation delay (ripple effect)

Circuit using JK Flip-Flops:
       ┌──────┐      ┌──────┐
J₀=1──│  JK  │──Q₀──│  JK  │──Q₁
K₀=1──│  FF0 │      │  FF1 │
CLK───┴──────┘  J₁──┴──────┘
                K₁

J₁ = K₁ = Q₀

State Table:
Q₁ Q₀ |  J₁K₁  J₀K₀ |  Next
 0  0  |   0X   11   |   01
 0  1  |   1X   11   |   10
 1  0  |   X0   11   |   11
 1  1  |   X1   11   |   00

BCD Counter:
Count: 0000 → 0001 → 0010 → ... → 1001 → 0000

IC 7490: Decade Counter chip

4-bit Ring Counter:

D-FF₀ → D-FF₁ → D-FF₂ → D-FF₃ →┐
  ↑                              │
  └──────────────────────────────┘

Sequence:
Q₃Q₂Q₁Q₀
1000 → 0100 → 0010 → 0001 → 1000...

Applications: State machines, sequence generators

4-bit Johnson Counter:

D-FF₀ → D-FF₁ → D-FF₂ → D-FF₃ →┐
  ↑                             NOT
  └──────────────────────────────┘

Sequence (8 states):
0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000

4-bit PIPO Register:

D₃──D-FF₃──Q₃    D₂──D-FF₂──Q₂    D₁──D-FF₁──Q₁    D₀──D-FF₀──Q₀
       │              │              │              │
    CLK ─────────────────────────────────────────────

All data loaded at once on clock edge
All data read at once

4-bit SISO (Right Shift):

DIN ── D-FF₀ ─ D-FF₁ ─ D-FF₂ ─ D-FF₃ ── DOUT
         │       │       │       │
      CLK ──────────────────────────

Example: Input 1011 (MSB first)
CLK  State
 0   0000  (Initial)
 1   1000  (Input 1)
 2   1100  (Input 0)
 3   1110  (Input 1)
 4   1111  (Input 1)

Application: UART receiver, SPI communication

Application: UART transmitter, data serialization

Mode Select (S₁S₀):
S₁ S₀ |  Operation
0  0  |  No change (Hold)
0  1  |  Shift Right
1  0  |  Shift Left
1  1  |  Parallel Load

IC 74195: 4-bit universal shift register

Memory Hierarchy:

                Memory
                  │
        ┌─────────┴─────────┐
        │                   │
     Volatile            Non-Volatile
    (RAM)                (ROM)
        │                   │
   ┌────┴────┐         ┌────┴────┐
   │         │         │         │
 SRAM     DRAM       ROM      EPROM
                               EEPROM
                               Flash

Example: 1K × 8 Memory

1K = 1024 words
8 = 8 bits per word

Total capacity: 1024 × 8 = 8192 bits = 8 Kb = 1 KB

Address lines needed: log₂(1024) = 10 lines
Data lines: 8 lines

Memory Block Diagram:

A₀-A₉ (10 lines)  ────┐
                      │ 1K×8
CS (Chip Select) ─────┤ Memory ──── D₀-D₇ (8 lines)
R/W̄ (Read/Write) ─────┤
                      └

Address Range: 0x000 to 0x3FF (0 to 1023)

Example: Create 1K×16 using two 1K×8 chips

A₀-A₉ ──┬─── 1K×8 ──── D₀-D₇
        │    Chip 1
CS  ────┼─── 1K×8 ──── D₈-D₁₅
        │    Chip 2
R/W̄ ────┘

Same addresses, more data bits

Example: Create 2K×8 using two 1K×8 chips

A₀-A₉ ──┬─── 1K×8 ──┐
        │    Chip 1 ├─── D₀-D₇
A₁₀ ────┤            │
Decoder │    1K×8 ───┘
        └─── Chip 2

A₁₀=0: Chip 1 (0x000-0x3FF)
A₁₀=1: Chip 2 (0x400-0x7FF)

Linear Decoding (Simple but wasteful):

A₁₀ ──NOT── CS̄₁ (Chip 1: A₁₀=0)
A₁₀ ──────── CS̄₂ (Chip 2: A₁₀=1)

Full Decoding (Using Decoder):

A₁₀-A₁₁ ───┐
           2:4      CS̄₀ → Chip 0
          Decoder   CS̄₁ → Chip 1
                    CS̄₂ → Chip 2
                    CS̄₃ → Chip 3

Memory Read Timing Diagram:

Address ──┐ Valid Address     ┌───
          └───────────────────┘

CS̄    ────┐                  ┌───
           └──────────────────┘

R/W̄   ────────────────────────── (High for Read)

Data  ────────┐ Valid Data ┌─────
              └────────────┘

         ←─ tACC ─→  (Access Time)

tACC: Time from address valid to data valid

Address ──┐ Valid Address     ┌───
          └───────────────────┘

CS̄    ────┐                  ┌───
           └──────────────────┘

R/W̄   ────┐                  ┌─── (Low for Write)
           └──────────────────┘

Data  ─────┐ Valid Data      ┌────
           └─────────────────┘

         ←─ tWR ─→  (Write Time)

     B
A    0   1
  ┌─────────
0 │  0   1
1 │  2   3

Example: F(A,B) = Σm(1,2,3)

     B
A    0   1
  ┌─────────
0 │  0   1
1 │  1   1

Grouping:
Group 1 (1,3): B
Group 2 (2,3): A

F = A + B

       BC
A     00  01  11  10
   ┌───────────────
 0 │  0   1   3   2
 1 │  4   5   7   6

Example: F(A,B,C) = Σm(1,3,5,7)

       BC
A     00  01  11  10
   ┌───────────────
 0 │  0   1   1   0
 1 │  0   1   1   0

Grouping: Vertical column (1,3,5,7)
F = C

Gray code ordering! (00,01,11,10)

         CD
AB      00  01  11  10
     ┌──────────────────
 00  │  0   1   3   2
 01  │  4   5   7   6
 11  │ 12  13  15  14
 10  │  8   9  11  10

Rules for Grouping:
1. Group size: 1, 2, 4, 8, 16 (powers of 2)
2. Groups should be rectangular
3. Make largest possible groups
4. Groups can overlap
5. Groups can wrap around edges
6. Minimize number of groups

F(A,B,C,D) = Σm(0,2,5,7,8,10,13,15)

         CD
AB      00  01  11  10
     ┌──────────────────
 00  │  1   0   0   1      Group 1: m(0,2,8,10) = B'D'
 01  │  0   1   1   0      Group 2: m(5,7,13,15) = BD
 11  │  0   1   1   0
 10  │  1   0   0   1

F = B'D' + BD = B ⊕ D

F(A,B,C) = Σm(1,3,7) + d(5,6)
d = don't care (can be 0 or 1)

Use X strategically to make larger groups!

       BC
A     00  01  11  10
   ┌───────────────
 0 │  0   1   1   0
 1 │  0   X   1   X

Include d(5) in group with m(1,7)
F = C

Example: F(A,B,C) = Σm(1,3,5,6,7)

Step 1: List by number of 1s
Group 0: m₁ = 001
Group 1: m₃ = 011
         m₅ = 101
Group 2: m₆ = 110
         m₇ = 111

Step 2: Combine (differ by 1 bit)
m₁,m₃: 0-1  (BC)
m₁,m₅: -01  (A'C)
m₃,m₇: -11  (BC)
m₅,m₇: 1-1  (AC)
m₆,m₇: 11-  (AB)

Step 3: Prime Implicants
BC, A'C, AC, AB

Step 4: Minimum cover
F = A'C + AB + BC

PLD Structure:

Inputs → AND Array → OR Array → Outputs

PAL: Programmable AND, Fixed OR
PLA: Programmable AND, Programmable OR
PROM: Fixed AND, Programmable OR

┌───────────────────────────────┐
│  CLB   CLB   CLB   CLB   CLB  │
│   │     │     │     │     │   │
│  CLB   CLB   CLB   CLB   CLB  │ ← Configurable Logic Blocks
│   │     │     │     │     │   │
│  CLB   CLB   CLB   CLB   CLB  │
└───────────────────────────────┘
        Programmable Interconnects

Each CLB contains:
- Look-Up Tables (LUTs) for logic
- Flip-flops for storage
- Multiplexers for routing

// 2-to-1 Multiplexer in Verilog
module mux2to1 (
    input a, b, sel,
    output y
);
    assign y = sel ? b : a;
endmodule

-- 2-to-1 Multiplexer in VHDL
entity mux2to1 is
    port (a, b, sel : in std_logic;
          y : out std_logic);
end mux2to1;

architecture behav of mux2to1 is
begin
    y <= b when sel = '1' else a;
end behav;

1. Specification
   Define requirements, features, constraints
       ↓
2. Architecture Design
   Block diagrams, high-level design
       ↓
3. RTL Design (HDL Coding)
   Write Verilog/VHDL code
       ↓
4. Simulation & Verification
   Testbenches, functional verification
       ↓
5. Synthesis
   Convert HDL to gate-level netlist
       ↓
6. Place & Route
   Map logic to physical layout
       ↓
7. Timing Analysis
   Check timing constraints, optimize
       ↓
8. Bitstream Generation
   Create configuration file for FPGA
       ↓
9. Programming & Testing
   Load onto hardware, test in real environment

Timing Diagram:

CLK   ──┐   ┌─────┐   ┌─
        └───┘     └───┘

DATA  ──────┐         ┌──
            └─────────┘

        ←tsu→ ←th→
            ↑ CLK edge

Violation:
- Setup Violation: Data changes too close to clock edge
- Hold Violation: Data changes too soon after clock edge

Maximum Clock Frequency:

fmax = 1 / (tCQ + tlogic + tsu)

Where:
tCQ = Clock-to-Q delay of source FF
tlogic = Combinational logic delay
tsu = Setup time of destination FF

Example:
tCQ = 2 ns, tlogic = 8 ns, tsu = 1 ns
fmax = 1 / (2+8+1) ns = 1/11 ns = 90.9 MHz

Dynamic Power:
P = C × V² × f × α

C = Load capacitance
V = Supply voltage
f = Clock frequency
α = Switching activity factor (0 to 1)

Reducing Power:
- Lower voltage
- Reduce clock frequency
- Clock gating (disable unused blocks)
- Power gating (turn off unused blocks)